{"id":"https://openalex.org/W1573681037","doi":"https://doi.org/10.1109/iwsoc.2003.1213066","title":"Symbolic simulation as a simplifying strategy for SoC verification","display_name":"Symbolic simulation as a simplifying strategy for SoC verification","publication_year":2004,"publication_date":"2004-04-23","ids":{"openalex":"https://openalex.org/W1573681037","doi":"https://doi.org/10.1109/iwsoc.2003.1213066","mag":"1573681037"},"language":"en","primary_location":{"id":"doi:10.1109/iwsoc.2003.1213066","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwsoc.2003.1213066","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071935946","display_name":"Emil Dumitrescu","orcid":"https://orcid.org/0000-0001-6614-4873"},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"E. Dumitrescu","raw_affiliation_strings":["TIMA Laboratory, Grenoble, France","TIMA Lab., Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA Lab., Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063371658","display_name":"D. Borrione","orcid":"https://orcid.org/0000-0002-4856-453X"},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"D. Borrione","raw_affiliation_strings":["TIMA Laboratory, Grenoble, France","TIMA Lab., Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA Lab., Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210087012"],"apc_list":null,"apc_paid":null,"fwci":0.2249,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.39672939,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1703","issue":null,"first_page":"378","last_page":"383"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.8305809497833252},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.789413571357727},{"id":"https://openalex.org/keywords/symbolic-trajectory-evaluation","display_name":"Symbolic trajectory evaluation","score":0.7599321603775024},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.5611443519592285},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5318911671638489},{"id":"https://openalex.org/keywords/class","display_name":"Class (philosophy)","score":0.487298846244812},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3890610933303833},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.32308429479599},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.2001529335975647},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07614219188690186}],"concepts":[{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.8305809497833252},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.789413571357727},{"id":"https://openalex.org/C23123167","wikidata":"https://www.wikidata.org/wiki/Q7661193","display_name":"Symbolic trajectory evaluation","level":3,"score":0.7599321603775024},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.5611443519592285},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5318911671638489},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.487298846244812},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3890610933303833},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.32308429479599},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2001529335975647},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07614219188690186},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iwsoc.2003.1213066","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwsoc.2003.1213066","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-00014148v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00014148","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings-3rd-IEEE-International-Workshop-on-System-on-Chip-for-Real-Time-Applications., 2003, Calgary, Alta., Canada. pp.378-83","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6100000143051147,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W240055707","https://openalex.org/W1488659932","https://openalex.org/W1503170978","https://openalex.org/W1547100201","https://openalex.org/W1576344789","https://openalex.org/W2024148935","https://openalex.org/W2059510773","https://openalex.org/W2080267935","https://openalex.org/W2112128273","https://openalex.org/W2122004390","https://openalex.org/W2150309803","https://openalex.org/W2161677825","https://openalex.org/W4241233758","https://openalex.org/W4244665469","https://openalex.org/W6629100741","https://openalex.org/W6825856664"],"related_works":["https://openalex.org/W2365988016","https://openalex.org/W1785234853","https://openalex.org/W2038864046","https://openalex.org/W1742935137","https://openalex.org/W1545972740","https://openalex.org/W2156717832","https://openalex.org/W1852145007","https://openalex.org/W4312733571","https://openalex.org/W1483297389","https://openalex.org/W1547517160"],"abstract_inverted_index":{"The":[0,54],"successful":[1],"application":[2],"of":[3,14,28,42,72],"model-checking":[4],"to":[5],"industrial":[6,83],"designs":[7],"requires":[8],"methods":[9],"for":[10,23],"reducing":[11],"the":[12,15,39,69,73],"complexity":[13],"model.":[16],"This":[17,63],"paper":[18],"presents":[19],"an":[20,33,46],"original":[21],"strategy,":[22],"a":[24,43,81],"well":[25],"identified":[26],"class":[27],"circuit":[29],"behaviors;":[30],"by":[31],"running":[32],"appropriate":[34],"symbolic":[35],"simulation":[36],"pattern":[37],"before":[38],"actual":[40,55],"proof":[41],"temporal":[44],"formula,":[45],"important":[47],"FSM":[48],"model":[49,56,75],"simplification":[50],"can":[51],"be":[52],"obtained.":[53],"reduction":[57],"step":[58],"is":[59],"formalized":[60],"and":[61,78],"illustrated.":[62],"method":[64],"has":[65],"been":[66],"implemented":[67],"within":[68],"CMU":[70],"version":[71],"SMV":[74],"checking":[76],"tool":[77],"validated":[79],"on":[80],"large":[82],"design.":[84]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}