{"id":"https://openalex.org/W2098656685","doi":"https://doi.org/10.1109/iwsoc.2003.1213053","title":"High-throughput switch-based interconnect for future SoCs","display_name":"High-throughput switch-based interconnect for future SoCs","publication_year":2004,"publication_date":"2004-04-23","ids":{"openalex":"https://openalex.org/W2098656685","doi":"https://doi.org/10.1109/iwsoc.2003.1213053","mag":"2098656685"},"language":"en","primary_location":{"id":"doi:10.1109/iwsoc.2003.1213053","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwsoc.2003.1213053","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078441163","display_name":"Partha Pratim Pande","orcid":"https://orcid.org/0000-0002-5930-8531"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"P.P. Pande","raw_affiliation_strings":["SoC Research Laboratory Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SoC Research Laboratory Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000193253","display_name":"Cristian Grecu","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"C. Grecu","raw_affiliation_strings":["SoC Research Laboratory Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SoC Research Laboratory Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062724257","display_name":"A. Ivanov","orcid":"https://orcid.org/0000-0002-0882-6750"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"A. Ivanov","raw_affiliation_strings":["SoC Research Laboratory Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SoC Research Laboratory Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111280120","display_name":"R. Saleh","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"R. Saleh","raw_affiliation_strings":["SoC Research Laboratory Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SoC Research Laboratory Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":2.2516,"has_fulltext":false,"cited_by_count":65,"citation_normalized_percentile":{"value":0.89676345,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"304","last_page":"310"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7415102124214172},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6990785002708435},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6553120613098145},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6138136386871338},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5674595832824707},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5012445449829102},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.47722867131233215},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.4519127309322357},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4474692642688751},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3913273513317108},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.35661619901657104},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10782209038734436},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.08966609835624695}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7415102124214172},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6990785002708435},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6553120613098145},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6138136386871338},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5674595832824707},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5012445449829102},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.47722867131233215},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4519127309322357},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4474692642688751},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3913273513317108},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.35661619901657104},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10782209038734436},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.08966609835624695},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iwsoc.2003.1213053","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwsoc.2003.1213053","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1939228150","https://openalex.org/W2051265155","https://openalex.org/W2096061336","https://openalex.org/W2097560795","https://openalex.org/W2105016642","https://openalex.org/W2119122672","https://openalex.org/W2119677480","https://openalex.org/W2123184444","https://openalex.org/W2140137324","https://openalex.org/W2141381960","https://openalex.org/W2146421115","https://openalex.org/W2160642395","https://openalex.org/W2162336594","https://openalex.org/W3169463464","https://openalex.org/W4248138030","https://openalex.org/W6677907928"],"related_works":["https://openalex.org/W2765822612","https://openalex.org/W1984658281","https://openalex.org/W2388672758","https://openalex.org/W2135981148","https://openalex.org/W2754086592","https://openalex.org/W2144357574","https://openalex.org/W2065289416","https://openalex.org/W3198758847","https://openalex.org/W4230458348","https://openalex.org/W1966325333"],"abstract_inverted_index":{"System":[0],"on":[1,28],"Chip":[2],"(SoC)":[3],"design":[4,86],"in":[5,44,126],"the":[6,12,29,41,105,121,131,135,151,156],"forthcoming":[7],"billion-transistor":[8],"era":[9],"will":[10],"involve":[11],"integration":[13,31],"of":[14,24,32,40,90,104,123,134,168],"numerous":[15],"heterogeneous":[16],"semiconductor":[17],"intellectual":[18],"property":[19],"(IP)":[20],"blocks.":[21],"The":[22],"success":[23],"this":[25,142],"approach":[26,84],"depends":[27],"seamless":[30],"cores":[33],"like":[34],"processors,":[35],"memories,":[36],"UARTs,":[37],"etc.":[38],"Some":[39],"main":[42],"problems":[43,76],"future":[45],"SoC":[46,136],"designs":[47],"arise":[48],"from":[49],"non":[50,70],"scalable":[51,71],"global":[52,58,91],"wire":[53],"delays,":[54],"failure":[55],"to":[56,62,85,115,161,163],"achieve":[57,141],"synchronization,":[59],"errors":[60],"due":[61,114],"signal":[63],"integrity":[64],"issues":[65],"and":[66],"difficulties":[67],"associated":[68],"with":[69,108],"bus-based":[72],"functional":[73],"interconnects.":[74],"These":[75],"can":[77,137,158],"be":[78,138,159],"addressed":[79],"by":[80,155],"using":[81,97],"a":[82,98,164,169],"network-centric":[83],"SoCs,":[87],"where":[88],"instead":[89],"wiring,":[92],"IP":[93],"blocks":[94],"are":[95],"integrated":[96],"switch-based":[99],"on-chip":[100,128],"interconnection":[101,109,129],"network.":[102],"One":[103],"major":[106],"concerns":[107],"networks":[110],"is":[111,148],"throughput":[112,133,143],"degradation":[113],"idle":[116],"physical":[117],"channels.":[118],"By":[119],"introducing":[120],"concept":[122],"virtual":[124],"channels":[125],"an":[127],"network,":[130],"overall":[132,152],"improved.":[139],"To":[140],"improvement,":[144],"extra":[145],"silicon":[146],"area":[147,153],"required":[149],"but":[150],"consumed":[154],"switches":[157],"made":[160],"amount":[162],"very":[165],"small":[166],"portion":[167],"billion":[170],"transistor":[171],"SoC.":[172]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":5},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":7},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":9}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
