{"id":"https://openalex.org/W2132388213","doi":"https://doi.org/10.1109/iwsoc.2003.1213036","title":"Pullpipelining: a technique for systolic pipelined circuits","display_name":"Pullpipelining: a technique for systolic pipelined circuits","publication_year":2004,"publication_date":"2004-03-01","ids":{"openalex":"https://openalex.org/W2132388213","doi":"https://doi.org/10.1109/iwsoc.2003.1213036","mag":"2132388213"},"language":"en","primary_location":{"id":"doi:10.1109/iwsoc.2003.1213036","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwsoc.2003.1213036","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025811150","display_name":"Oswaldo Cadenas","orcid":"https://orcid.org/0000-0003-4152-6458"},"institutions":[{"id":"https://openalex.org/I71052956","display_name":"University of Reading","ror":"https://ror.org/05v62cm79","country_code":"GB","type":"education","lineage":["https://openalex.org/I71052956"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"O. Cadenas","raw_affiliation_strings":["School of Systems Engineering, University of Reading, Reading, UK","Sch. of Syst. Eng., Reading Univ., , UK"],"affiliations":[{"raw_affiliation_string":"School of Systems Engineering, University of Reading, Reading, UK","institution_ids":["https://openalex.org/I71052956"]},{"raw_affiliation_string":"Sch. of Syst. Eng., Reading Univ., , UK","institution_ids":["https://openalex.org/I71052956"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051333590","display_name":"Graham M. Megson","orcid":null},"institutions":[{"id":"https://openalex.org/I71052956","display_name":"University of Reading","ror":"https://ror.org/05v62cm79","country_code":"GB","type":"education","lineage":["https://openalex.org/I71052956"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"G. Megson","raw_affiliation_strings":["School of Systems Engineering, University of Reading, Reading, UK","Sch. of Syst. Eng., Reading Univ., , UK"],"affiliations":[{"raw_affiliation_string":"School of Systems Engineering, University of Reading, Reading, UK","institution_ids":["https://openalex.org/I71052956"]},{"raw_affiliation_string":"Sch. of Syst. Eng., Reading Univ., , UK","institution_ids":["https://openalex.org/I71052956"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5025811150"],"corresponding_institution_ids":["https://openalex.org/I71052956"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.20042348,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"205","last_page":"210"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.8986386060714722},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7940966486930847},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7898544073104858},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7281951904296875},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6242583990097046},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5606184601783752},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.4978675842285156},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4841245114803314},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.47172656655311584},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.4603000283241272},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4168979525566101},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3602811098098755},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32619428634643555},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.31282228231430054},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2524767518043518},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.2150590419769287},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.10726705193519592},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10338035225868225}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.8986386060714722},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7940966486930847},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7898544073104858},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7281951904296875},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6242583990097046},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5606184601783752},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.4978675842285156},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4841245114803314},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.47172656655311584},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4603000283241272},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4168979525566101},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3602811098098755},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32619428634643555},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.31282228231430054},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2524767518043518},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.2150590419769287},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.10726705193519592},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10338035225868225},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iwsoc.2003.1213036","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwsoc.2003.1213036","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4099999964237213,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W80853866","https://openalex.org/W1514189495","https://openalex.org/W1555915743","https://openalex.org/W1561252668","https://openalex.org/W1577093684","https://openalex.org/W2021609618","https://openalex.org/W2043687377","https://openalex.org/W2143310750","https://openalex.org/W2145874611","https://openalex.org/W2169222350","https://openalex.org/W2171591485","https://openalex.org/W2295576379","https://openalex.org/W2725179571","https://openalex.org/W4231905827","https://openalex.org/W4255898989","https://openalex.org/W6633384124","https://openalex.org/W6661271325"],"related_works":["https://openalex.org/W2534955606","https://openalex.org/W2019183874","https://openalex.org/W4247613350","https://openalex.org/W2211833700","https://openalex.org/W2384756109","https://openalex.org/W1588764976","https://openalex.org/W1994289828","https://openalex.org/W2051103499","https://openalex.org/W2138197942","https://openalex.org/W2162743530"],"abstract_inverted_index":{"Pullpipelining,":[0],"a":[1,19,21,32,91],"pipeline":[2,41],"technique":[3],"where":[4],"data":[5],"is":[6,14,44,58],"pulled":[7],"from":[8,11],"successor":[9],"stages":[10,13,62],"predecessor":[12],"proposed.":[15],"Control":[16],"circuits":[17],"using":[18,46,90],"synchronous,":[20],"semisynchronous":[22],"and":[23],"an":[24],"asynchronous":[25],"approach":[26],"are":[27,66],"given.":[28],"Simulation":[29],"examples":[30],"for":[31],"DLX":[33],"generic":[34],"RISC":[35],"datapath":[36],"show":[37],"that":[38],"common":[39],"control":[40],"circuit":[42],"overhead":[43],"avoided":[45],"the":[47,64],"proposal.":[48],"Applications":[49],"to":[50,83],"linear":[51],"systolic":[52],"arrays":[53],"in":[54,63],"cases":[55],"when":[56],"computation":[57],"finished":[59],"at":[60],"early":[61],"array":[65],"foreseen.":[67],"This":[68,80],"would":[69],"allow":[70],"run-time":[71],"data-driven":[72],"digital":[73],"frequency":[74],"modulation":[75],"of":[76],"synchronous":[77,92],"pipelined":[78],"designs.":[79],"has":[81],"applications":[82],"implement":[84],"algorithms":[85],"exhibiting":[86],"average-case":[87],"processing":[88],"time":[89],"approach.":[93]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}