{"id":"https://openalex.org/W1586800869","doi":"https://doi.org/10.1109/iwsoc.2003.1213034","title":"RtrASSoc: an adaptable superscalar reconfigurable system-on-chip. The simulator","display_name":"RtrASSoc: an adaptable superscalar reconfigurable system-on-chip. The simulator","publication_year":2004,"publication_date":"2004-03-01","ids":{"openalex":"https://openalex.org/W1586800869","doi":"https://doi.org/10.1109/iwsoc.2003.1213034","mag":"1586800869"},"language":"en","primary_location":{"id":"doi:10.1109/iwsoc.2003.1213034","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwsoc.2003.1213034","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087439754","display_name":"Jorge Luiz e Silva","orcid":"https://orcid.org/0000-0003-1119-7323"},"institutions":[{"id":"https://openalex.org/I249163148","display_name":"Centro Universit\u00e1rio Eur\u00edpedes de Marilia","ror":"https://ror.org/02er3bg49","country_code":"BR","type":"facility","lineage":["https://openalex.org/I249163148"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"J.L. Silva","raw_affiliation_strings":["Funda\u00e7\u00e3o de Ensino Euripides Soares da Rocha, Sao Paulo, Brazil","Fundacao de Ensino Euripides Soares da Rocha, Programa de Pos-Graduaco em Ciencia da Computacao, Marilia, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Funda\u00e7\u00e3o de Ensino Euripides Soares da Rocha, Sao Paulo, Brazil","institution_ids":["https://openalex.org/I249163148"]},{"raw_affiliation_string":"Fundacao de Ensino Euripides Soares da Rocha, Programa de Pos-Graduaco em Ciencia da Computacao, Marilia, Brazil","institution_ids":["https://openalex.org/I249163148"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081121737","display_name":"Roberto Costa","orcid":null},"institutions":[{"id":"https://openalex.org/I4210109090","display_name":"Universidade Sagrado Cora\u00e7\u00e3o","ror":"https://ror.org/01thzqc78","country_code":"BR","type":"education","lineage":["https://openalex.org/I4210109090"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"R.M. Costa","raw_affiliation_strings":["Universidade do Sagrado Cora\u00e7\u00e3o USC, Sao Paulo, Brazil","Programa de P?s-Gradua??o em Ci?ncia da Computa??"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade do Sagrado Cora\u00e7\u00e3o USC, Sao Paulo, Brazil","institution_ids":["https://openalex.org/I4210109090"]},{"raw_affiliation_string":"Programa de P?s-Gradua??o em Ci?ncia da Computa??","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013911887","display_name":"G.H.R. Jorge","orcid":null},"institutions":[{"id":"https://openalex.org/I249163148","display_name":"Centro Universit\u00e1rio Eur\u00edpedes de Marilia","ror":"https://ror.org/02er3bg49","country_code":"BR","type":"facility","lineage":["https://openalex.org/I249163148"]},{"id":"https://openalex.org/I4210109090","display_name":"Universidade Sagrado Cora\u00e7\u00e3o","ror":"https://ror.org/01thzqc78","country_code":"BR","type":"education","lineage":["https://openalex.org/I4210109090"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"G.H.R. Jorge","raw_affiliation_strings":["Funda\u00e7\u00e3o de Ensino Euripides Soares da Rocha, Sao Paulo, Brazil","Universidade do Sagrado Cora??o de Jesus"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Funda\u00e7\u00e3o de Ensino Euripides Soares da Rocha, Sao Paulo, Brazil","institution_ids":["https://openalex.org/I249163148"]},{"raw_affiliation_string":"Universidade do Sagrado Cora??o de Jesus","institution_ids":["https://openalex.org/I4210109090"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.618,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.59692856,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":"294","issue":null,"first_page":"196","last_page":"200"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8030705451965332},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7249929308891296},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7237268686294556},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7076517343521118},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6872754693031311},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5735020637512207},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5433060526847839},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4893576502799988},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4271393120288849},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33529219031333923},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.24559053778648376}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8030705451965332},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7249929308891296},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7237268686294556},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7076517343521118},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6872754693031311},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5735020637512207},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5433060526847839},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4893576502799988},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4271393120288849},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33529219031333923},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.24559053778648376},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iwsoc.2003.1213034","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwsoc.2003.1213034","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W380633946","https://openalex.org/W1518937533","https://openalex.org/W1555915743","https://openalex.org/W1603586820","https://openalex.org/W1627535389","https://openalex.org/W1830708738","https://openalex.org/W1979547397","https://openalex.org/W2036409230","https://openalex.org/W2068041061","https://openalex.org/W2098378442","https://openalex.org/W2103518090","https://openalex.org/W2105863864","https://openalex.org/W2107546753","https://openalex.org/W2115294662","https://openalex.org/W2119131949","https://openalex.org/W2120942300","https://openalex.org/W2121903852","https://openalex.org/W2125055477","https://openalex.org/W2129402073","https://openalex.org/W2132173136","https://openalex.org/W2133408285","https://openalex.org/W2133776928","https://openalex.org/W2142490124","https://openalex.org/W2148663569","https://openalex.org/W2165099691","https://openalex.org/W2166907065","https://openalex.org/W2169601811","https://openalex.org/W2169996458","https://openalex.org/W2725179571","https://openalex.org/W3140993944","https://openalex.org/W4234831121","https://openalex.org/W4238797334","https://openalex.org/W4239023471","https://openalex.org/W4256282209","https://openalex.org/W6679958904","https://openalex.org/W6680057268"],"related_works":["https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2340647897","https://openalex.org/W2808484818","https://openalex.org/W1574948540"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"the":[3,40,73,79,83,88,97,100],"purpose":[4],"of":[5,39,99],"development":[6],"for":[7,90],"RtrASSoc,":[8],"an":[9],"Adaptable,":[10],"Superscalar":[11],"and":[12,29,58,86],"Reconfigurable":[13],"System":[14,56],"on":[15,33],"Chip.":[16],"The":[17,102],"RtrASSoc":[18],"will":[19,42,51,93,104],"be":[20,43,52,69,94,105],"used":[21,95],"in":[22,107,111],"Embedded":[23,54],"Systems":[24],"that":[25,92],"need":[26],"capacity,":[27],"performance,":[28],"low":[30],"cost,":[31],"based":[32],"Programmable":[34],"System-on-Chip":[35],"(PSOC),":[36],"where":[37,63],"part":[38,50,62],"system":[41,103],"a":[44,53,60,64,112],"embedded":[45],"superscalar":[46],"processor":[47],"(ESP),":[48],"another":[49],"Operating":[55],"(EOS),":[57],"finally":[59],"reconfigurable":[61,65,80],"routines":[66,81],"(RR)":[67],"can":[68],"reconfigured,":[70],"extracted":[71],"from":[72,82,115],"application":[74,84],"program.":[75],"A":[76],"C-compiler":[77],"extracts":[78],"program":[85],"fix":[87],"parameters":[89],"reconfiguration":[91],"during":[96],"execution":[98],"application.":[101],"tested":[106],"recognition":[108],"pattern":[109],"applications":[110],"FPGA":[113],"Virtex":[114],"Xilinx.":[116]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}