{"id":"https://openalex.org/W2162013772","doi":"https://doi.org/10.1109/iwsoc.2003.1213018","title":"Application specific coarse-grained FPGA for processing element in real time parallel particle filters","display_name":"Application specific coarse-grained FPGA for processing element in real time parallel particle filters","publication_year":2004,"publication_date":"2004-03-02","ids":{"openalex":"https://openalex.org/W2162013772","doi":"https://doi.org/10.1109/iwsoc.2003.1213018","mag":"2162013772"},"language":"en","primary_location":{"id":"doi:10.1109/iwsoc.2003.1213018","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwsoc.2003.1213018","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004722651","display_name":"Magesh Sadasivam","orcid":"https://orcid.org/0000-0001-9752-5695"},"institutions":[{"id":"https://openalex.org/I1327163397","display_name":"State University of New York","ror":"https://ror.org/01q1z8k08","country_code":"US","type":"education","lineage":["https://openalex.org/I1327163397"]},{"id":"https://openalex.org/I59553526","display_name":"Stony Brook University","ror":"https://ror.org/05qghxh33","country_code":"US","type":"education","lineage":["https://openalex.org/I59553526"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Sadasivam","raw_affiliation_strings":["Mobile Systems Design Laboratory, Department of Electrical and Computer Engineering, State University of New York, Stony Brook, Stony Brook, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mobile Systems Design Laboratory, Department of Electrical and Computer Engineering, State University of New York, Stony Brook, Stony Brook, NY, USA","institution_ids":["https://openalex.org/I1327163397","https://openalex.org/I59553526"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111980806","display_name":"Sanjing Hong","orcid":null},"institutions":[{"id":"https://openalex.org/I1327163397","display_name":"State University of New York","ror":"https://ror.org/01q1z8k08","country_code":"US","type":"education","lineage":["https://openalex.org/I1327163397"]},{"id":"https://openalex.org/I59553526","display_name":"Stony Brook University","ror":"https://ror.org/05qghxh33","country_code":"US","type":"education","lineage":["https://openalex.org/I59553526"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanjing Hong","raw_affiliation_strings":["Mobile Systems Design Laboratory, Department of Electrical and Computer Engineering, State University of New York, Stony Brook, Stony Brook, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mobile Systems Design Laboratory, Department of Electrical and Computer Engineering, State University of New York, Stony Brook, Stony Brook, NY, USA","institution_ids":["https://openalex.org/I1327163397","https://openalex.org/I59553526"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.824,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.69330069,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"116","last_page":"119"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9822999835014343,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9822999835014343,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9815999865531921,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9765999913215637,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8593913316726685},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.7337688207626343},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.7000101804733276},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6848495006561279},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5378317832946777},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4993586540222168},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42295122146606445},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40012794733047485},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38116806745529175},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3594006299972534},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.05473208427429199}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8593913316726685},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.7337688207626343},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.7000101804733276},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6848495006561279},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5378317832946777},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4993586540222168},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42295122146606445},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40012794733047485},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38116806745529175},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3594006299972534},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.05473208427429199},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iwsoc.2003.1213018","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwsoc.2003.1213018","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1483307070","https://openalex.org/W1587911018","https://openalex.org/W1939643391","https://openalex.org/W2111490093","https://openalex.org/W2168634963","https://openalex.org/W4285719527","https://openalex.org/W6640605051"],"related_works":["https://openalex.org/W1612076744","https://openalex.org/W2152074211","https://openalex.org/W2126857316","https://openalex.org/W2129019972","https://openalex.org/W3164085601","https://openalex.org/W1967938402","https://openalex.org/W1522032972","https://openalex.org/W2139962137","https://openalex.org/W2113308450","https://openalex.org/W2386041993"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"application":[4],"specific":[5],"reconfigurable":[6,34,45],"architecture":[7,18,41,66],"based":[8],"on":[9],"coarse-grain":[10],"FPGA":[11],"for":[12,47],"real-time":[13],"parallel":[14],"particle":[15],"filters.":[16],"The":[17,39,64],"consists":[19],"of":[20,23,54,59],"a":[21],"set":[22],"heterogeneous":[24],"arithmetic":[25],"units":[26,46],"and":[27,44,62],"buffer":[28],"banks,":[29],"where":[30],"their":[31],"interconnections":[32],"are":[33],"at":[35],"the":[36,55],"hardware":[37],"level.":[38],"proposed":[40,65],"separates":[42],"fixed":[43],"high-throughput":[48],"realization.":[49],"We":[50],"compare":[51],"potential":[52],"throughput":[53],"design":[56],"with":[57],"that":[58],"commercial":[60],"FPGAs":[61],"DSPs.":[63],"is":[67],"implemented":[68],"in":[69],"0.25":[70],"/spl":[71],"mu/m":[72],"CMOS":[73],"process.":[74]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}