{"id":"https://openalex.org/W2135392710","doi":"https://doi.org/10.1109/iwrsp.2002.1029748","title":"System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures","display_name":"System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2135392710","doi":"https://doi.org/10.1109/iwrsp.2002.1029748","mag":"2135392710"},"language":"en","primary_location":{"id":"doi:10.1109/iwrsp.2002.1029748","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwrsp.2002.1029748","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 13th IEEE International Workshop on Rapid System Prototyping","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003178960","display_name":"M\u00e1rio V\u00e9stias","orcid":"https://orcid.org/0000-0001-8556-4507"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"M.P. Vestias","raw_affiliation_strings":["INESC/IST, Portugal","IST, INESC, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC/IST, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"IST, INESC, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062555847","display_name":"Hor\u00e1cio C. Neto","orcid":"https://orcid.org/0000-0002-3621-8322"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"H.C. Neto","raw_affiliation_strings":["INESC/IST, Portugal","IST, INESC, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC/IST, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"IST, INESC, Portugal","institution_ids":["https://openalex.org/I121345201"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I121345201"],"apc_list":null,"apc_paid":null,"fwci":0.6974,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.68472906,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"220","issue":null,"first_page":"130","last_page":"137"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.9596705436706543},{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.9164804220199585},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8273510932922363},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5885757803916931},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5698701739311218},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5662698745727539},{"id":"https://openalex.org/keywords/dataflow-architecture","display_name":"Dataflow architecture","score":0.5549097657203674},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4888729453086853},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4437873363494873},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.42403554916381836},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.34249186515808105},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3321874737739563},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.28736889362335205},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12338367104530334}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.9596705436706543},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.9164804220199585},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8273510932922363},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5885757803916931},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5698701739311218},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5662698745727539},{"id":"https://openalex.org/C176727019","wikidata":"https://www.wikidata.org/wiki/Q1172415","display_name":"Dataflow architecture","level":3,"score":0.5549097657203674},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4888729453086853},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4437873363494873},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.42403554916381836},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.34249186515808105},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3321874737739563},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.28736889362335205},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12338367104530334},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iwrsp.2002.1029748","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwrsp.2002.1029748","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 13th IEEE International Workshop on Rapid System Prototyping","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W849719210","https://openalex.org/W1582450315","https://openalex.org/W1582823543","https://openalex.org/W2024060531","https://openalex.org/W2024678563","https://openalex.org/W2070563545","https://openalex.org/W2072358147","https://openalex.org/W2084825390","https://openalex.org/W2087656024","https://openalex.org/W2095409492","https://openalex.org/W2097911714","https://openalex.org/W2128286183","https://openalex.org/W2138959668","https://openalex.org/W2164123397","https://openalex.org/W3150544384","https://openalex.org/W4243459916","https://openalex.org/W6680693484"],"related_works":["https://openalex.org/W2564598376","https://openalex.org/W1484403103","https://openalex.org/W2584408851","https://openalex.org/W2115158825","https://openalex.org/W2101960124","https://openalex.org/W2783505431","https://openalex.org/W2521947294","https://openalex.org/W2135392710","https://openalex.org/W2461217932","https://openalex.org/W2134941280"],"abstract_inverted_index":{"We":[0,53],"present":[1],"a":[2,9],"system-level":[3],"co-synthesis":[4,19,56],"tool":[5,20],"as":[6],"part":[7],"of":[8,14],"methodology":[10],"for":[11],"the":[12,73,81],"co-design":[13],"dataflow":[15,28],"dominated":[16],"systems.":[17],"The":[18,76],"uses":[21],"an":[22,36],"applicational":[23],"model":[24,38],"that":[25,39,58,80],"supports":[26],"iterative":[27],"graphs":[29],"with":[30,61],"hierarchical":[31],"tasks":[32],"and":[33,35,43,46,68],"feedback,":[34],"architectural":[37],"considers":[40],"extended":[41,63],"interconnection":[42],"memory":[44],"topologies":[45],"takes":[47],"into":[48],"account":[49],"reconfigurable":[50],"computing":[51],"units.":[52],"describe":[54],"new":[55,82],"techniques":[57],"deal":[59],"effectively":[60],"these":[62],"models":[64],"while":[65],"applying":[66],"retiming":[67],"unrolling":[69],"loops":[70],"to":[71,87],"optimize":[72],"execution":[74],"time.":[75],"preliminary":[77],"results":[78],"indicate":[79],"approach":[83],"proposed":[84],"is":[85],"able":[86],"efficiently":[88],"handle":[89],"real":[90],"problems.":[91]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}