{"id":"https://openalex.org/W2169975643","doi":"https://doi.org/10.1109/iwrsp.1996.506801","title":"Implementing DSP applications on heterogeneous targets using minimal size data buffers","display_name":"Implementing DSP applications on heterogeneous targets using minimal size data buffers","publication_year":2002,"publication_date":"2002-12-23","ids":{"openalex":"https://openalex.org/W2169975643","doi":"https://doi.org/10.1109/iwrsp.1996.506801","mag":"2169975643"},"language":"en","primary_location":{"id":"doi:10.1109/iwrsp.1996.506801","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwrsp.1996.506801","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Seventh IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003913326","display_name":"M. Ad\u00e9","orcid":null},"institutions":[{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"M. Ade","raw_affiliation_strings":["ESAT Department, ACCA Laboratory Kard, Katholieke Universiteit Leuven, Heverlee, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ESAT Department, ACCA Laboratory Kard, Katholieke Universiteit Leuven, Heverlee, Belgium","institution_ids":["https://openalex.org/I99464096"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039430610","display_name":"Rudy Lauwereins","orcid":"https://orcid.org/0000-0002-3861-0168"},"institutions":[{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"R. Lauwereins","raw_affiliation_strings":["ESAT Department, ACCA Laboratory Kard, Katholieke Universiteit Leuven, Heverlee, Belgium","Katholieke Universiteit Leuven, Leuven, Flanders, BE"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ESAT Department, ACCA Laboratory Kard, Katholieke Universiteit Leuven, Heverlee, Belgium","institution_ids":["https://openalex.org/I99464096"]},{"raw_affiliation_string":"Katholieke Universiteit Leuven, Leuven, Flanders, BE","institution_ids":["https://openalex.org/I99464096"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038782909","display_name":"J.A. Peperstrate","orcid":null},"institutions":[{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"J.A. Peperstrate","raw_affiliation_strings":["ESAT, Katholieke Univ., Leuven, Heverlee, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ESAT, Katholieke Univ., Leuven, Heverlee, Belgium","institution_ids":["https://openalex.org/I99464096"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I99464096"],"apc_list":null,"apc_paid":null,"fwci":0.9545,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.75599304,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"166","last_page":"172"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.7783874869346619},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7777106761932373},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7641962766647339},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.7594177722930908},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.6121178865432739},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.5467547178268433},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5193089842796326},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48011350631713867},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.42532432079315186},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.41482940316200256},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4082548916339874},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34282052516937256},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.1982954740524292},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0963699221611023}],"concepts":[{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.7783874869346619},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7777106761932373},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7641962766647339},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7594177722930908},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.6121178865432739},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.5467547178268433},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5193089842796326},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48011350631713867},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.42532432079315186},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.41482940316200256},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4082548916339874},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34282052516937256},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.1982954740524292},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0963699221611023},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iwrsp.1996.506801","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwrsp.1996.506801","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Seventh IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320318240","display_name":"European Space Agency","ror":"https://ror.org/03wd9za21"},{"id":"https://openalex.org/F4320324232","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1496267491","https://openalex.org/W1860183717","https://openalex.org/W1917952890","https://openalex.org/W2042607638","https://openalex.org/W2070385897","https://openalex.org/W2111327768","https://openalex.org/W2120431055","https://openalex.org/W2134603416","https://openalex.org/W2155256384","https://openalex.org/W2168964723","https://openalex.org/W2179825846","https://openalex.org/W6629762304"],"related_works":["https://openalex.org/W2154523322","https://openalex.org/W2083200807","https://openalex.org/W1603137082","https://openalex.org/W2364195017","https://openalex.org/W2355430452","https://openalex.org/W2049983405","https://openalex.org/W2392315374","https://openalex.org/W1854591799","https://openalex.org/W1528221867","https://openalex.org/W1969049073"],"abstract_inverted_index":{"The":[0,32],"paper":[1],"presents":[2],"an":[3,42],"algorithm":[4,34],"to":[5],"determine":[6],"the":[7,25,37,45,67,77],"smallest":[8],"possible":[9],"data":[10,16,70],"buffer":[11],"sizes":[12],"for":[13,44],"arbitrary":[14,56],"synchronous":[15],"flow":[17,39],"(SDF)":[18],"applications,":[19],"such":[20],"that":[21],"we":[22],"can":[23],"guarantee":[24],"existence":[26],"of":[27,40,49,60,69,73],"a":[28],"deadlock":[29],"free":[30],"schedule.":[31],"presented":[33],"fits":[35],"in":[36],"design":[38],"GRAPE,":[41],"environment":[43],"emulation":[46],"and":[47,64],"implementation":[48],"digital":[50],"signal":[51],"processing":[52],"(DSP)":[53],"systems":[54],"on":[55,82],"target":[57],"architectures,":[58],"consisting":[59],"programmable":[61],"DSP":[62],"processors":[63],"FPGAs.":[65],"Reducing":[66],"size":[68],"buffers":[71],"is":[72],"high":[74],"importance":[75],"when":[76],"application":[78],"will":[79],"be":[80],"mapped":[81],"Field":[83],"Programmable":[84],"Gate":[85],"Arrays":[86],"(FPGA),":[87],"since":[88],"register":[89],"resources":[90],"are":[91],"rather":[92],"scarce.":[93]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}