{"id":"https://openalex.org/W2962917147","doi":"https://doi.org/10.1109/iwcmc.2019.8766730","title":"Impact of Clustering Algorithms on the performance of Multilevel Switch Boxes FPGA with Long Wires","display_name":"Impact of Clustering Algorithms on the performance of Multilevel Switch Boxes FPGA with Long Wires","publication_year":2019,"publication_date":"2019-06-01","ids":{"openalex":"https://openalex.org/W2962917147","doi":"https://doi.org/10.1109/iwcmc.2019.8766730","mag":"2962917147"},"language":"en","primary_location":{"id":"doi:10.1109/iwcmc.2019.8766730","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwcmc.2019.8766730","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 15th International Wireless Communications &amp; Mobile Computing Conference (IWCMC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049692974","display_name":"Khouloud Bouaziz","orcid":"https://orcid.org/0000-0003-0770-1419"},"institutions":[{"id":"https://openalex.org/I4210119561","display_name":"Digital Research Centre of Sfax","ror":"https://ror.org/02s48dm85","country_code":"TN","type":"facility","lineage":["https://openalex.org/I4210119561"]}],"countries":["TN"],"is_corresponding":false,"raw_author_name":"Khouloud Bouaziz","raw_affiliation_strings":["Digital Research Center of Sfax, Sfax, Tunisia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Digital Research Center of Sfax, Sfax, Tunisia","institution_ids":["https://openalex.org/I4210119561"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024841287","display_name":"Sonda Chtourou","orcid":"https://orcid.org/0000-0001-5669-242X"},"institutions":[{"id":"https://openalex.org/I4210131288","display_name":"National Engineering School of Tunis","ror":"https://ror.org/03b1zjt31","country_code":"TN","type":"education","lineage":["https://openalex.org/I4210131288","https://openalex.org/I63596082"]}],"countries":["TN"],"is_corresponding":false,"raw_author_name":"Sonda Chtourou","raw_affiliation_strings":["CES Research Laboratory, National Engineering School of Sfax"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CES Research Laboratory, National Engineering School of Sfax","institution_ids":["https://openalex.org/I4210131288"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026522015","display_name":"Mohamed Abid","orcid":"https://orcid.org/0000-0001-7409-292X"},"institutions":[{"id":"https://openalex.org/I4210119561","display_name":"Digital Research Centre of Sfax","ror":"https://ror.org/02s48dm85","country_code":"TN","type":"facility","lineage":["https://openalex.org/I4210119561"]}],"countries":["TN"],"is_corresponding":false,"raw_author_name":"Mohamed Abid","raw_affiliation_strings":["Digital Research Center of Sfax, Sfax, Tunisia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Digital Research Center of Sfax, Sfax, Tunisia","institution_ids":["https://openalex.org/I4210119561"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111822030","display_name":"Zied Marrakchi","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zied Marrakchi","raw_affiliation_strings":["Mentor Graphics, Tunis, Tunisia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics, Tunis, Tunisia","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109086263","display_name":"Abdulfattah M. Obeid","orcid":null},"institutions":[{"id":"https://openalex.org/I1284598098","display_name":"King Abdulaziz City for Science and Technology","ror":"https://ror.org/05tdz6m39","country_code":"SA","type":"facility","lineage":["https://openalex.org/I1284598098"]}],"countries":["SA"],"is_corresponding":false,"raw_author_name":"Abdulfattah M. Obeid","raw_affiliation_strings":["CITRI, KACST, Riyadh, Saudi Arabia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CITRI, KACST, Riyadh, Saudi Arabia","institution_ids":["https://openalex.org/I1284598098"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06040986,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"497","issue":null,"first_page":"1025","last_page":"1030"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9095432758331299},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.7153696417808533},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7127988934516907},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5012097358703613},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.48308876156806946},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.471607506275177},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.44542282819747925},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.43706780672073364},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.42938846349716187},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4264363646507263},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40379369258880615},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.35125482082366943},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2491668462753296},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15914589166641235},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10742610692977905},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10513538122177124},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08355399966239929}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9095432758331299},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.7153696417808533},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7127988934516907},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5012097358703613},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.48308876156806946},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.471607506275177},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.44542282819747925},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.43706780672073364},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.42938846349716187},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4264363646507263},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40379369258880615},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.35125482082366943},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2491668462753296},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15914589166641235},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10742610692977905},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10513538122177124},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08355399966239929},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iwcmc.2019.8766730","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwcmc.2019.8766730","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 15th International Wireless Communications &amp; Mobile Computing Conference (IWCMC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1523051745","https://openalex.org/W1967128905","https://openalex.org/W1977850862","https://openalex.org/W2002641171","https://openalex.org/W2033685698","https://openalex.org/W2047199967","https://openalex.org/W2077892593","https://openalex.org/W2078174680","https://openalex.org/W2083637347","https://openalex.org/W2111756578","https://openalex.org/W2113645429","https://openalex.org/W2122724240","https://openalex.org/W2128473621","https://openalex.org/W2149513075","https://openalex.org/W2150281391","https://openalex.org/W2157761128","https://openalex.org/W2168493238","https://openalex.org/W2275304190","https://openalex.org/W2293079373","https://openalex.org/W3023858524","https://openalex.org/W4246219036","https://openalex.org/W4246961877","https://openalex.org/W4252890894","https://openalex.org/W6682237558"],"related_works":["https://openalex.org/W2366961778","https://openalex.org/W1572721274","https://openalex.org/W2019936863","https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W1977171228"],"abstract_inverted_index":{"Computer-Aided":[0],"Design":[1],"(CAD)":[2],"tools":[3],"represent":[4],"a":[5],"major":[6],"factor":[7],"to":[8,23,32,43,83,108],"enhance":[9],"the":[10,51,62,75,84],"quality":[11],"of":[12,53,64,77,86],"Field":[13],"Programmable":[14],"Gate":[15],"Arrays":[16],"(FPGAs)":[17],"and":[18,39,55,105],"use":[19],"their":[20,24],"architectural":[21],"resources":[22],"full":[25],"potential.":[26],"Since":[27],"they":[28],"can":[29],"be":[30],"developed":[31],"satisfy":[33],"application":[34],"constraints":[35],"like":[36],"surface,":[37],"speed":[38],"energy":[40,106],"while":[41],"responding":[42],"Time-to-market":[44],"requirements.":[45],"In":[46],"this":[47],"paper,":[48],"we":[49],"explore":[50],"impact":[52],"T-VPack":[54],"First":[56],"Choice":[57],"(FC)":[58],"clustering":[59],"algorithms":[60],"on":[61,90],"performance":[63,76],"Multilevel":[65],"Switch":[66],"Boxes":[67],"(MS)":[68],"FPGA":[69,79,91],"with":[70],"Long":[71],"Wires":[72],"(LWs).":[73],"Indeed,":[74],"an":[78],"is":[80],"highly":[81],"sensitive":[82],"mapping":[85],"Logic":[87],"Blocks":[88],"(LBs)":[89],"architecture.":[92],"This":[93],"work":[94],"shows":[95],"that":[96],"FC":[97],"ameliorates":[98],"power":[99],"consumption,":[100],"area,":[101],"critical":[102],"path":[103],"delay":[104],"compared":[107],"T-VPack.":[109]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
