{"id":"https://openalex.org/W3126000872","doi":"https://doi.org/10.1109/itc44778.2020.9325261","title":"At-speed DfT Architecture for Bundled-data Design","display_name":"At-speed DfT Architecture for Bundled-data Design","publication_year":2020,"publication_date":"2020-11-01","ids":{"openalex":"https://openalex.org/W3126000872","doi":"https://doi.org/10.1109/itc44778.2020.9325261","mag":"3126000872"},"language":"en","primary_location":{"id":"doi:10.1109/itc44778.2020.9325261","is_oa":false,"landing_page_url":"https://doi.org/10.1109/itc44778.2020.9325261","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://hal.science/hal-03352862/document","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070461364","display_name":"Ricardo Aquino Guazzelli","orcid":null},"institutions":[{"id":"https://openalex.org/I4210129773","display_name":"Institute of Engineering","ror":"https://ror.org/03ny67e60","country_code":"NP","type":"education","lineage":["https://openalex.org/I155028946","https://openalex.org/I4210129773"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]},{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]}],"countries":["FR","NP"],"is_corresponding":true,"raw_author_name":"Ricardo Aquino Guazzelli","raw_affiliation_strings":["CNRS, Grenoble INP* TIMA, Univ. Grenoble Alpes, Grenoble, France","Institute of Engineering Univ., Grenoble, Alpes"],"affiliations":[{"raw_affiliation_string":"CNRS, Grenoble INP* TIMA, Univ. Grenoble Alpes, Grenoble, France","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I899635006","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"Institute of Engineering Univ., Grenoble, Alpes","institution_ids":["https://openalex.org/I4210129773"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038428972","display_name":"Laurent Fesquet","orcid":"https://orcid.org/0000-0002-6045-8510"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I4210129773","display_name":"Institute of Engineering","ror":"https://ror.org/03ny67e60","country_code":"NP","type":"education","lineage":["https://openalex.org/I155028946","https://openalex.org/I4210129773"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR","NP"],"is_corresponding":false,"raw_author_name":"Laurent Fesquet","raw_affiliation_strings":["CNRS, Grenoble INP* TIMA, Univ. Grenoble Alpes, Grenoble, France","Institute of Engineering Univ., Grenoble, Alpes"],"affiliations":[{"raw_affiliation_string":"CNRS, Grenoble INP* TIMA, Univ. Grenoble Alpes, Grenoble, France","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I899635006","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"Institute of Engineering Univ., Grenoble, Alpes","institution_ids":["https://openalex.org/I4210129773"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5070461364"],"corresponding_institution_ids":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I4210129773","https://openalex.org/I899635006"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.1563105,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7410508394241333},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5777896642684937},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.5596842169761658},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.5143888592720032},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.49109339714050293},{"id":"https://openalex.org/keywords/controllability","display_name":"Controllability","score":0.4634304940700531},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4345752000808716},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4276077151298523},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4189662039279938},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3534349799156189},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34016233682632446},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.23747405409812927},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.21604076027870178},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16377821564674377},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.12279382348060608},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1041496992111206},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10331279039382935}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7410508394241333},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5777896642684937},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.5596842169761658},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.5143888592720032},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.49109339714050293},{"id":"https://openalex.org/C48209547","wikidata":"https://www.wikidata.org/wiki/Q1331104","display_name":"Controllability","level":2,"score":0.4634304940700531},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4345752000808716},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4276077151298523},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4189662039279938},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3534349799156189},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34016233682632446},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.23747405409812927},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.21604076027870178},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16377821564674377},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.12279382348060608},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1041496992111206},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10331279039382935},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C28826006","wikidata":"https://www.wikidata.org/wiki/Q33521","display_name":"Applied mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/itc44778.2020.9325261","is_oa":false,"landing_page_url":"https://doi.org/10.1109/itc44778.2020.9325261","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-03352862v1","is_oa":true,"landing_page_url":"https://hal.science/hal-03352862","pdf_url":"https://hal.science/hal-03352862/document","source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc","license_id":"https://openalex.org/licenses/cc-by-nc","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEELink","raw_type":"Conference papers"}],"best_oa_location":{"id":"pmh:oai:HAL:hal-03352862v1","is_oa":true,"landing_page_url":"https://hal.science/hal-03352862","pdf_url":"https://hal.science/hal-03352862/document","source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc","license_id":"https://openalex.org/licenses/cc-by-nc","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEELink","raw_type":"Conference papers"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3126000872.pdf","grobid_xml":"https://content.openalex.org/works/W3126000872.grobid-xml"},"referenced_works_count":33,"referenced_works":["https://openalex.org/W1483902580","https://openalex.org/W1486202357","https://openalex.org/W1542879788","https://openalex.org/W1559109967","https://openalex.org/W1589327193","https://openalex.org/W2053931020","https://openalex.org/W2087107264","https://openalex.org/W2096906056","https://openalex.org/W2105632996","https://openalex.org/W2107163997","https://openalex.org/W2109020844","https://openalex.org/W2110259743","https://openalex.org/W2110477287","https://openalex.org/W2110967082","https://openalex.org/W2111813487","https://openalex.org/W2120280394","https://openalex.org/W2120511589","https://openalex.org/W2127003363","https://openalex.org/W2150872535","https://openalex.org/W2151098223","https://openalex.org/W2159380800","https://openalex.org/W2161331676","https://openalex.org/W2163578050","https://openalex.org/W2166402441","https://openalex.org/W2167871424","https://openalex.org/W2178247634","https://openalex.org/W2296552982","https://openalex.org/W2487142227","https://openalex.org/W2529177493","https://openalex.org/W2799246403","https://openalex.org/W2908473507","https://openalex.org/W4234485851","https://openalex.org/W6674720022"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2164493372","https://openalex.org/W2114980936","https://openalex.org/W2142405811","https://openalex.org/W1594445436","https://openalex.org/W2128920253","https://openalex.org/W2164349885","https://openalex.org/W1768820276","https://openalex.org/W1589327193"],"abstract_inverted_index":{"At-speed":[0],"testing":[1,120,126,163],"for":[2,24,128,140,165],"asynchronous":[3,129],"circuits":[4,130],"is":[5],"still":[6],"an":[7,161],"open":[8],"concern":[9],"in":[10,39,56,97,131,187,204,219],"the":[11,36,43,67,98,124,132,137,153,170,183,191,196,205],"literature.":[12],"Due":[13],"to":[14,41,115,216],"its":[15,116],"timing":[16,68,193],"constraints":[17,69],"between":[18,70],"control":[19,31,71,99,154,188],"and":[20,32,60,72,100,107,207],"data":[21,33,73,101,156,167,197],"paths,":[22,102],"Design":[23],"Testability":[25],"(DfT)":[26],"methodologies":[27,127,150],"must":[28,75],"test":[29,178],"both":[30],"paths":[34,74,189],"at":[35],"same":[37],"time":[38],"order":[40],"guarantee":[42],"circuit":[44,54,222],"correctness.":[45],"As":[46],"Process":[47],"Voltage":[48],"Temperature":[49],"(PVT)":[50],"variations":[51],"significantly":[52],"impact":[53],"design":[55],"newer":[57],"CMOS":[58],"technologies":[59],"low-power":[61],"techniques":[62,139],"such":[63],"as":[64],"voltage":[65],"scaling,":[66],"be":[76],"tested":[77],"after":[78],"fabrication":[79],"not":[80,105,108],"only":[81],"under":[82],"nominal":[83],"conditions":[84],"but":[85],"through":[86,224],"a":[87,111],"range":[88],"of":[89,176,195,210],"operating":[90],"conditions.":[91],"However,":[92],"this":[93,177,213],"requirement":[94],"demands":[95],"modifications":[96],"which":[103],"are":[104],"straightforward":[106],"desirable":[109],"from":[110,146],"commercial":[112],"standpoint":[113],"due":[114],"incompatibility":[117],"with":[118,123],"conventional":[119],"tools.":[121],"Even":[122],"available":[125,225],"literature":[133],"-":[134,148],"by":[135],"adapting":[136],"existing":[138],"synchronous":[141],"or":[142,155],"creating":[143],"new":[144],"ones":[145],"scratch":[147],"those":[149],"usually":[151],"target":[152,175],"path.":[157],"This":[158],"work":[159,214],"explores":[160],"at-speed":[162],"approach":[164,179],"bundled":[166],"circuits,":[168],"targeting":[169],"micropipeline":[171],"template.":[172],"The":[173],"main":[174],"focuses":[180],"on":[181],"whether":[182],"sized":[184],"delay":[185],"lines":[186],"respect":[190],"local":[192],"assumptions":[194],"paths.":[198],"By":[199],"adding":[200],"extra":[201],"controllability":[202],"points":[203],"controllers":[206],"taking":[208],"advantage":[209],"scan-chain":[211],"structures,":[212],"targets":[215],"generate/stall":[217],"tokens":[218],"controllers,":[220],"enabling":[221],"verification":[223],"scan":[226],"chains.":[227]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2025-10-10T00:00:00"}