{"id":"https://openalex.org/W3125862252","doi":"https://doi.org/10.1109/itc44778.2020.9325247","title":"Flip-flops fanout splitting in scan designs","display_name":"Flip-flops fanout splitting in scan designs","publication_year":2020,"publication_date":"2020-11-01","ids":{"openalex":"https://openalex.org/W3125862252","doi":"https://doi.org/10.1109/itc44778.2020.9325247","mag":"3125862252"},"language":"en","primary_location":{"id":"doi:10.1109/itc44778.2020.9325247","is_oa":false,"landing_page_url":"https://doi.org/10.1109/itc44778.2020.9325247","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068477218","display_name":"Maxim Ladnushkin","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Maxim Ladnushkin","raw_affiliation_strings":["Microcircuits topology design and synthesis departament, Federal State Institution \u00abScientific Research Institute for System Analysis of the Russian Academy of Sciences\u00bb, Moscow, Russia"],"affiliations":[{"raw_affiliation_string":"Microcircuits topology design and synthesis departament, Federal State Institution \u00abScientific Research Institute for System Analysis of the Russian Academy of Sciences\u00bb, Moscow, Russia","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5068477218"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.231,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.52569686,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":"c 23","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.8306317329406738},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.6295361518859863},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5707311630249023},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.5517652630805969},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5249010324478149},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3896613121032715},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.35811758041381836},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35767751932144165},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.34406691789627075},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3433927297592163},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25630009174346924},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1143697202205658},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10986021161079407}],"concepts":[{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.8306317329406738},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.6295361518859863},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5707311630249023},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.5517652630805969},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5249010324478149},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3896613121032715},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.35811758041381836},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35767751932144165},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.34406691789627075},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3433927297592163},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25630009174346924},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1143697202205658},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10986021161079407},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/itc44778.2020.9325247","is_oa":false,"landing_page_url":"https://doi.org/10.1109/itc44778.2020.9325247","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1863819993","https://openalex.org/W1969318341","https://openalex.org/W2008990681","https://openalex.org/W2040588226","https://openalex.org/W2062746030","https://openalex.org/W2097417935","https://openalex.org/W2104107023","https://openalex.org/W2106203961","https://openalex.org/W2107960880","https://openalex.org/W2127737927","https://openalex.org/W2131432014","https://openalex.org/W2134998505","https://openalex.org/W2145392290","https://openalex.org/W2146356977","https://openalex.org/W2149601343","https://openalex.org/W2159871346","https://openalex.org/W2167639389","https://openalex.org/W2726285617","https://openalex.org/W2947266479","https://openalex.org/W2979722875","https://openalex.org/W4234199418","https://openalex.org/W4252615853","https://openalex.org/W6639197171","https://openalex.org/W6675787411"],"related_works":["https://openalex.org/W4285708951","https://openalex.org/W2147986372","https://openalex.org/W2786111245","https://openalex.org/W1979305473","https://openalex.org/W3009953521","https://openalex.org/W4234763172","https://openalex.org/W2992024382","https://openalex.org/W2125317684","https://openalex.org/W1588361197","https://openalex.org/W2161045522"],"abstract_inverted_index":{"Test":[0],"point":[1],"insertion":[2],"is":[3],"a":[4,29],"key":[5],"method":[6,31,82],"of":[7,13,32,50,75,98],"circuit":[8],"modification":[9],"for":[10],"significant":[11],"reduction":[12,58],"test":[14,19,39,43,76,84],"patterns":[15,77],"during":[16],"an":[17],"automatic":[18],"pattern":[20],"generation":[21],"in":[22,35,63],"scan":[23,51],"compression":[24,74],"designs.":[25,66],"This":[26,53],"paper":[27],"presents":[28],"new":[30],"flip-flops":[33],"replication":[34],"order":[36],"to":[37,88],"reduce":[38],"data":[40],"volume":[41],"and":[42,59],"application":[44,85],"time":[45,86],"by":[46],"splitting":[47],"the":[48,80],"fanout":[49,57,61],"cells.":[52],"proposed":[54,81],"approach":[55],"employs":[56],"reconvergent":[60],"elimination":[62],"large":[64],"nanometer":[65],"Experimental":[67],"results":[68],"on":[69],"several":[70],"IP-designs":[71],"with":[72,92],"embedded":[73],"show":[78],"that":[79],"reduces":[83],"up":[87],"nearly":[89],"2":[90],"times":[91],"hardware":[93],"costs":[94],"not":[95],"exceeding":[96],"2.5%":[97],"design":[99],"area.":[100]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}