{"id":"https://openalex.org/W3124612390","doi":"https://doi.org/10.1109/itc44778.2020.9325240","title":"SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts","display_name":"SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts","publication_year":2020,"publication_date":"2020-11-01","ids":{"openalex":"https://openalex.org/W3124612390","doi":"https://doi.org/10.1109/itc44778.2020.9325240","mag":"3124612390"},"language":"en","primary_location":{"id":"doi:10.1109/itc44778.2020.9325240","is_oa":false,"landing_page_url":"https://doi.org/10.1109/itc44778.2020.9325240","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070763111","display_name":"Sujay Pandey","orcid":"https://orcid.org/0000-0002-9745-9330"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Sujay Pandey","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078866149","display_name":"Zhiwei Liao","orcid":"https://orcid.org/0000-0002-1246-0050"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhiwei Liao","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042978605","display_name":"Shreyas Nandi","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shreyas Nandi","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110668867","display_name":"Sanya Gupta","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanya Gupta","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113724917","display_name":"Suriyaprakash Natarajan","orcid":"https://orcid.org/0000-0002-5499-4341"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Suriyaprakash Natarajan","raw_affiliation_strings":["Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101770488","display_name":"Arani Sinha","orcid":"https://orcid.org/0000-0003-2069-3177"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arani Sinha","raw_affiliation_strings":["Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104362993","display_name":"Adit D. Singh","orcid":null},"institutions":[{"id":"https://openalex.org/I82497590","display_name":"Auburn University","ror":"https://ror.org/02v80fc35","country_code":"US","type":"education","lineage":["https://openalex.org/I82497590"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Adit Singh","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Auburn University, Atlanta, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Auburn University, Atlanta, USA","institution_ids":["https://openalex.org/I82497590"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069579193","display_name":"Abhijit Chatterjee","orcid":"https://orcid.org/0000-0003-1553-4470"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Abhijit Chatterjee","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5070763111"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":1.1552,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.78469803,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.8277059197425842},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.824191689491272},{"id":"https://openalex.org/keywords/resistive-touchscreen","display_name":"Resistive touchscreen","score":0.7261049747467041},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6007694602012634},{"id":"https://openalex.org/keywords/code-coverage","display_name":"Code coverage","score":0.5155951380729675},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5103077292442322},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4756086468696594},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4742155075073242},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.45995843410491943},{"id":"https://openalex.org/keywords/test-suite","display_name":"Test suite","score":0.4385167956352234},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.42469415068626404},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4221828579902649},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38021111488342285},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.30402958393096924},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23076295852661133},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18361935019493103},{"id":"https://openalex.org/keywords/test-case","display_name":"Test case","score":0.16512414813041687},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.08212652802467346}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.8277059197425842},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.824191689491272},{"id":"https://openalex.org/C6899612","wikidata":"https://www.wikidata.org/wiki/Q852911","display_name":"Resistive touchscreen","level":2,"score":0.7261049747467041},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6007694602012634},{"id":"https://openalex.org/C53942775","wikidata":"https://www.wikidata.org/wiki/Q1211721","display_name":"Code coverage","level":3,"score":0.5155951380729675},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5103077292442322},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4756086468696594},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4742155075073242},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.45995843410491943},{"id":"https://openalex.org/C151552104","wikidata":"https://www.wikidata.org/wiki/Q7705809","display_name":"Test suite","level":4,"score":0.4385167956352234},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.42469415068626404},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4221828579902649},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38021111488342285},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.30402958393096924},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23076295852661133},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18361935019493103},{"id":"https://openalex.org/C128942645","wikidata":"https://www.wikidata.org/wiki/Q1568346","display_name":"Test case","level":3,"score":0.16512414813041687},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.08212652802467346},{"id":"https://openalex.org/C152877465","wikidata":"https://www.wikidata.org/wiki/Q208042","display_name":"Regression analysis","level":2,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/itc44778.2020.9325240","is_oa":false,"landing_page_url":"https://doi.org/10.1109/itc44778.2020.9325240","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6499999761581421,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1667775840","https://openalex.org/W1840416799","https://openalex.org/W1989858431","https://openalex.org/W2008990681","https://openalex.org/W2019500818","https://openalex.org/W2021085718","https://openalex.org/W2042655082","https://openalex.org/W2089323087","https://openalex.org/W2098169468","https://openalex.org/W2102556246","https://openalex.org/W2112559786","https://openalex.org/W2121476155","https://openalex.org/W2132188866","https://openalex.org/W2135613306","https://openalex.org/W2136159433","https://openalex.org/W2143459771","https://openalex.org/W2152406824","https://openalex.org/W2160444875","https://openalex.org/W2165929878","https://openalex.org/W2169294720","https://openalex.org/W2541342484","https://openalex.org/W2586685023","https://openalex.org/W2810128013","https://openalex.org/W3008582674","https://openalex.org/W3141622555","https://openalex.org/W6638781664","https://openalex.org/W6675373693"],"related_works":["https://openalex.org/W3088373974","https://openalex.org/W2507920222","https://openalex.org/W2059954071","https://openalex.org/W2544301500","https://openalex.org/W2014831604","https://openalex.org/W1996761806","https://openalex.org/W2040178082","https://openalex.org/W2386366670","https://openalex.org/W2102513613","https://openalex.org/W2152415903"],"abstract_inverted_index":{"Recent":[0],"advances":[1],"in":[2,7,43],"process":[3,15],"technology":[4],"have":[5],"resulted":[6],"novel":[8],"defect":[9,31,53,66,77,156,159],"mechanisms":[10],"making":[11],"the":[12,127,130,137],"test":[13,107,152],"generation":[14,108],"very":[16],"challenging.":[17],"In":[18],"addition":[19],"to":[20,72,80,123,126],"complete":[21,93],"opens":[22,36],"and":[23,37,100,142,148],"shorts":[24,38],"that":[25,60,91,118],"can":[26],"be":[27,124],"represented":[28],"via":[29,129],"extreme":[30],"resistance":[32],"magnitudes,":[33],"partial":[34,97],"resistive":[35],"are":[39,63,166],"also":[40],"of":[41,84,140],"concern":[42],"deeply":[44],"scaled":[45],"CMOS":[46],"technologies.":[47],"For":[48],"open":[49,99],"defects":[50,74],"with":[51,75,146],"intermediate":[52,76],"magnitude":[54,78],"values,":[55],"it":[56],"has":[57],"been":[58],"shown":[59],"multi-pattern":[61,85,121],"tests":[62,86,122,165],"necessary":[64],"for":[65,87,110,154],"exposure.":[67],"We":[68],"extend":[69],"this":[70],"approach":[71,109],"short":[73,101],"values":[79],"obtain":[81],"a":[82],"suite":[83],"standard":[88],"cell":[89],"instances":[90],"cover":[92],"as":[94,96],"well":[95],"intra-cell":[98],"defects.":[102],"A":[103,133],"hierarchical":[104],"scan-compatible":[105],"SAT-based":[106],"full":[111],"scan":[112,131,150],"sequential":[113],"circuits":[114],"is":[115,136],"then":[116],"proposed":[117],"allows":[119],"such":[120],"applied":[125],"circuit":[128],"infrastructure.":[132],"key":[134],"innovation":[135],"combined":[138],"use":[139],"shift":[141],"capture":[143],"operations":[144],"along":[145],"launch-on-capture":[147],"launch-on-shift":[149],"based":[151],"application":[153],"increased":[155],"coverage.":[157],"Resulting":[158],"coverage":[160],"improvements":[161],"over":[162],"conventional":[163],"two-pattern":[164],"demonstrated":[167],"on":[168],"ISCAS89":[169],"benchmark":[170],"circuits.":[171]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}