{"id":"https://openalex.org/W2767217438","doi":"https://doi.org/10.1109/itc-asia.2017.8097109","title":"A run-pause-resume silicon debug technique for multiple clock domain systems","display_name":"A run-pause-resume silicon debug technique for multiple clock domain systems","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2767217438","doi":"https://doi.org/10.1109/itc-asia.2017.8097109","mag":"2767217438"},"language":"en","primary_location":{"id":"doi:10.1109/itc-asia.2017.8097109","is_oa":false,"landing_page_url":"https://doi.org/10.1109/itc-asia.2017.8097109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Test Conference in Asia (ITC-Asia)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016083347","display_name":"Shuo-Lian Hong","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shuo-Lian Hong","raw_affiliation_strings":["Dept. of Electrical Engineering, National Cheng Kung University, Taiwan","Department of Electrical Engineering , National Cheng Kung University , Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering, National Cheng Kung University, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"Department of Electrical Engineering , National Cheng Kung University , Taiwan","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5079657769","display_name":"Kuen-Jong Lee","orcid":"https://orcid.org/0000-0002-6690-0074"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Kuen-Jong Lee","raw_affiliation_strings":["Dept. of Electrical Engineering, National Cheng Kung University, Taiwan","Department of Electrical Engineering , National Cheng Kung University , Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering, National Cheng Kung University, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"Department of Electrical Engineering , National Cheng Kung University , Taiwan","institution_ids":["https://openalex.org/I91807558"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2924,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.61305438,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"46","last_page":"51"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.8466158509254456},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7872486710548401},{"id":"https://openalex.org/keywords/background-debug-mode-interface","display_name":"Background debug mode interface","score":0.767454206943512},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5573973655700684},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5276241302490234},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.520347535610199},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5114354491233826},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.47198134660720825},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.448725163936615},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.4217541515827179},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.41966792941093445},{"id":"https://openalex.org/keywords/sync","display_name":"sync","score":0.4166179299354553},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.37169772386550903},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3637349605560303},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3262026906013489},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1701221764087677},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.14244726300239563},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.093361496925354}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.8466158509254456},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7872486710548401},{"id":"https://openalex.org/C124774103","wikidata":"https://www.wikidata.org/wiki/Q4839640","display_name":"Background debug mode interface","level":3,"score":0.767454206943512},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5573973655700684},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5276241302490234},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.520347535610199},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5114354491233826},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.47198134660720825},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.448725163936615},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.4217541515827179},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.41966792941093445},{"id":"https://openalex.org/C3913047","wikidata":"https://www.wikidata.org/wiki/Q1956265","display_name":"sync","level":3,"score":0.4166179299354553},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.37169772386550903},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3637349605560303},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3262026906013489},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1701221764087677},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.14244726300239563},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.093361496925354},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/itc-asia.2017.8097109","is_oa":false,"landing_page_url":"https://doi.org/10.1109/itc-asia.2017.8097109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Test Conference in Asia (ITC-Asia)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322795","display_name":"Ministry of Science and Technology, Taiwan","ror":"https://ror.org/02kv4zf79"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1967690711","https://openalex.org/W2112041422","https://openalex.org/W2119616711","https://openalex.org/W2119677575","https://openalex.org/W2121357476","https://openalex.org/W2129981070","https://openalex.org/W2142295179","https://openalex.org/W2143592276","https://openalex.org/W2155538747","https://openalex.org/W2157212773","https://openalex.org/W2162925013","https://openalex.org/W2163953032","https://openalex.org/W2293773707","https://openalex.org/W2550814511","https://openalex.org/W2555734087","https://openalex.org/W2576406381","https://openalex.org/W4251579334","https://openalex.org/W4285719527","https://openalex.org/W6678346030"],"related_works":["https://openalex.org/W4386968318","https://openalex.org/W2474747038","https://openalex.org/W2137310043","https://openalex.org/W3006003651","https://openalex.org/W2294981364","https://openalex.org/W2052455055","https://openalex.org/W2040807843","https://openalex.org/W2337711143","https://openalex.org/W2384600254","https://openalex.org/W2169622190"],"abstract_inverted_index":{"The":[0],"run-pause-resume":[1],"(RPR)":[2],"debug":[3,27,88,129,177],"methodology":[4],"allows":[5],"one":[6],"to":[7,37,95,100,106,116,121,154],"pause":[8,102,119,155],"the":[9,14,22,84,97,107,118,126,132,136,158,168],"normal":[10,23],"circuit":[11,127],"operations,":[12],"observe":[13],"internal":[15],"states":[16],"of":[17,87,135],"flip-flops":[18,52],"and":[19,63,110,131,156,175],"then":[20],"resume":[21,157],"operations":[24],"for":[25,125],"further":[26],"process.":[28],"Data":[29],"invalidation":[30,82,148],"is":[31,93,114,172,179],"a":[32,42,54,74,111],"major":[33],"problem":[34,49],"that":[35,78,167],"needs":[36],"be":[38,66],"addressed":[39],"when":[40,51],"debugging":[41],"multiple-clock":[43],"design":[44],"with":[45,83],"this":[46,70],"methodology.":[47],"This":[48],"occurs":[50],"in":[53],"receiving":[55],"clock":[56,137,162],"domain":[57,138],"capture":[58],"incorrect":[59],"data":[60,81,133,147],"during":[61],"debugging,":[62],"thus":[64],"cannot":[65],"resumed":[67],"correctly.":[68],"In":[69],"paper":[71],"we":[72,144],"propose":[73],"novel":[75],"RPR":[76],"technique":[77],"can":[79,145],"avoid":[80,146],"cycle-level":[85],"granularity":[86],"resolution.":[89],"A":[90],"software":[91],"program":[92],"employed":[94],"calculate":[96],"exact":[98],"time":[99],"transmit":[101],"control":[103],"signals":[104,124],"according":[105],"user-defined":[108],"breakpoint":[109],"hardware":[112,169],"controller":[113],"developed":[115],"convert":[117],"signal":[120],"appropriate":[122],"gating":[123],"under":[128],"(CUD)":[130],"path":[134],"crossing":[139],"interface.":[140],"By":[141],"doing":[142],"this,":[143],"as":[149,151],"well":[150],"allow":[152],"users":[153],"CUD":[159],"at":[160],"arbitrary":[161],"cycle.":[163],"Experimental":[164],"results":[165],"show":[166],"area":[170],"overhead":[171],"very":[173],"small":[174],"100%":[176],"resolution":[178],"achieved.":[180]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}