{"id":"https://openalex.org/W4413755465","doi":"https://doi.org/10.1109/isvlsi65124.2025.11130342","title":"Efficient modulo 2n\u20134 arithmetic units","display_name":"Efficient modulo 2n\u20134 arithmetic units","publication_year":2025,"publication_date":"2025-07-06","ids":{"openalex":"https://openalex.org/W4413755465","doi":"https://doi.org/10.1109/isvlsi65124.2025.11130342"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi65124.2025.11130342","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi65124.2025.11130342","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058346543","display_name":"D. Bakalis","orcid":"https://orcid.org/0009-0003-0875-072X"},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Dimitris Bakalis","raw_affiliation_strings":["University of Patras,Department of Physics,Patras,Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Patras,Department of Physics,Patras,Greece","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065912730","display_name":"H.T. Vergos","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Haridimos T. Vergos","raw_affiliation_strings":["University of Patras,Department of Computer Engineering &#x0026; Informatics,Patras,Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Patras,Department of Computer Engineering &#x0026; Informatics,Patras,Greece","institution_ids":["https://openalex.org/I174878644"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I174878644"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17614161,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.9940999746322632,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.9940999746322632,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11166","display_name":"Analytic Number Theory Research","score":0.982699990272522,"subfield":{"id":"https://openalex.org/subfields/2602","display_name":"Algebra and Number Theory"},"field":{"id":"https://openalex.org/fields/26","display_name":"Mathematics"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11797","display_name":"graph theory and CDMA systems","score":0.965399980545044,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/modulo","display_name":"Modulo","score":0.6604763269424438},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.6253969669342041},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4178427457809448},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3213801383972168},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.31114429235458374},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.2631222605705261}],"concepts":[{"id":"https://openalex.org/C54732982","wikidata":"https://www.wikidata.org/wiki/Q1415345","display_name":"Modulo","level":2,"score":0.6604763269424438},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.6253969669342041},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4178427457809448},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3213801383972168},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.31114429235458374},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.2631222605705261}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvlsi65124.2025.11130342","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi65124.2025.11130342","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W177760375","https://openalex.org/W1771562617","https://openalex.org/W1971928471","https://openalex.org/W1978292082","https://openalex.org/W1981011893","https://openalex.org/W1998961262","https://openalex.org/W2008084314","https://openalex.org/W2050337180","https://openalex.org/W2075158086","https://openalex.org/W2087096176","https://openalex.org/W2105867649","https://openalex.org/W2110979084","https://openalex.org/W2129841790","https://openalex.org/W2143462372","https://openalex.org/W2789516105","https://openalex.org/W2799995256","https://openalex.org/W2923392082","https://openalex.org/W2991012113","https://openalex.org/W3080933033","https://openalex.org/W4206624899","https://openalex.org/W4243810185","https://openalex.org/W4244281090","https://openalex.org/W4327809036","https://openalex.org/W4381743479","https://openalex.org/W4396893475","https://openalex.org/W4402215745","https://openalex.org/W4402835747","https://openalex.org/W4403446857"],"related_works":["https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W4391375266","https://openalex.org/W2117548279","https://openalex.org/W2097470475","https://openalex.org/W2070252991","https://openalex.org/W2807449856","https://openalex.org/W2941201715","https://openalex.org/W2025727968","https://openalex.org/W4297742300"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"novel":[3],"and":[4,14,63],"efficient":[5,48],"architectures":[6,35],"for":[7,36],"modulo":[8,11,15,25,37],"$2^{n}-4$":[9,12,16,26],"adders,":[10],"multipliers,":[13],"residue":[17],"generators":[18],"that":[19,54],"exploit":[20],"the":[21,55],"intrinsic":[22],"characteristics":[23],"of":[24],"arithmetic.":[27],"The":[28],"proposed":[29,56],"designs":[30],"are":[31],"derived":[32],"from":[33],"existing":[34],"$2^{n-2}-1$":[38],"operations,":[39],"supplemented":[40],"with":[41],"simple":[42],"logic":[43],"components,":[44],"thereby":[45],"enabling":[46],"highly":[47],"VLSI":[49],"implementations.":[50],"Experimental":[51],"comparisons":[52],"validate":[53],"circuits":[57],"offer":[58],"substantial":[59],"improvements":[60],"in":[61],"delay":[62],"area":[64],"over":[65],"previously":[66],"reported":[67],"designs.":[68]},"counts_by_year":[],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}
