{"id":"https://openalex.org/W4413755347","doi":"https://doi.org/10.1109/isvlsi65124.2025.11130276","title":"VFMA: Scalable Floating-Point Accelerator for Vector FMA on FPGAs","display_name":"VFMA: Scalable Floating-Point Accelerator for Vector FMA on FPGAs","publication_year":2025,"publication_date":"2025-07-06","ids":{"openalex":"https://openalex.org/W4413755347","doi":"https://doi.org/10.1109/isvlsi65124.2025.11130276"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi65124.2025.11130276","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi65124.2025.11130276","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Himanshu Kumar Rai","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Himanshu Kumar Rai","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022406732","display_name":"S. Yadavalli","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sasi Snigdha Yadavalli","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":null,"display_name":"Aishwarya Sridhar","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Aishwarya Sridhar","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5101502774","display_name":"Nanditha Rao","orcid":"https://orcid.org/0000-0003-2369-0836"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nanditha Rao","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.27556237,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9825000166893005,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9825000166893005,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9469000101089478,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9452000260353088,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7874880433082581},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6737644076347351},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.670009970664978},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.6468262672424316},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5600312948226929},{"id":"https://openalex.org/keywords/point","display_name":"Point (geometry)","score":0.45648714900016785},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37136173248291016},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.34591639041900635},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3380434215068817},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17359387874603271},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11586266756057739}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7874880433082581},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6737644076347351},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.670009970664978},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.6468262672424316},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5600312948226929},{"id":"https://openalex.org/C28719098","wikidata":"https://www.wikidata.org/wiki/Q44946","display_name":"Point (geometry)","level":2,"score":0.45648714900016785},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37136173248291016},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.34591639041900635},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3380434215068817},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17359387874603271},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11586266756057739},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvlsi65124.2025.11130276","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi65124.2025.11130276","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8299999833106995}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1511879361","https://openalex.org/W2056540348","https://openalex.org/W2122454150","https://openalex.org/W2134123573","https://openalex.org/W2153753267","https://openalex.org/W2207050309","https://openalex.org/W2224617858","https://openalex.org/W2257139249","https://openalex.org/W2626303320","https://openalex.org/W3010779629","https://openalex.org/W3113606433","https://openalex.org/W3196381798","https://openalex.org/W4316658886","https://openalex.org/W4360615553","https://openalex.org/W4384833495","https://openalex.org/W4389491861","https://openalex.org/W4399659750"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2316202402","https://openalex.org/W1967938402","https://openalex.org/W3028347934","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2185692674"],"abstract_inverted_index":{"Floating-point":[0],"units":[1],"(FPUs)":[2],"provide":[3],"a":[4,41,65,118],"flexible":[5],"approach":[6],"to":[7,31,70,163],"numerical":[8],"computations,":[9],"particularly":[10],"in":[11],"applications":[12],"requiring":[13],"varying":[14],"levels":[15],"of":[16,115,137],"precision.":[17,144],"Operations":[18],"such":[19],"as":[20],"Fused":[21],"Multiply-Add":[22],"(FMA)":[23],"have":[24],"been":[25],"integrated":[26],"into":[27],"processor":[28],"instruction":[29],"sets":[30],"optimize":[32],"complex":[33],"arithmetic":[34],"tasks.":[35],"In":[36],"this":[37],"paper,":[38],"we":[39,63],"introduce":[40],"Vector":[42],"Floating-Point":[43],"FMA":[44],"(VFMA)":[45],"accelerator":[46,109,130],"on":[47,74,148],"an":[48,111,134],"FPGA":[49],"with":[50,110,131],"reconfigurable":[51],"lane":[52,113],"width":[53,114],"and":[54,59,152,159],"precision,":[55],"allowing":[56],"custom":[57],"exponent":[58],"mantissa":[60],"configurations.":[61],"Additionally,":[62],"propose":[64],"Tiled":[66],"VFMA":[67,85,108],"(TVFMA)":[68],"architecture":[69],"maximize":[71],"the":[72,75],"throughput":[73,89,122,136,155],"AMD-Xilinx":[76],"ZCU104":[77],"FPGA.":[78],"A":[79],"key":[80],"observation":[81],"is":[82],"that":[83],"DSP-based":[84],"designs":[86,97],"deliver":[87],"higher":[88,91,121,154],"at":[90,101],"precisions":[92,104],"(SP-32,":[93],"DP-64),":[94],"while":[95],"LUT-based":[96],"offer":[98],"comparable":[99],"performance":[100],"lower":[102],"bit":[103],"(BF-16,":[105],"QP-8).":[106],"The":[107,127],"optimal":[112],"vector-6":[116,132],"achieves":[117,133],"5.56":[119],"x":[120],"than":[123],"its":[124],"non-vector":[125],"counterpart.":[126],"proposed":[128],"TVFMA":[129],"impressive":[135],"$633.2":[138],"\\mathrm{GFLOP}":[139],"/":[140],"\\mathrm{s}$":[141],"for":[142,156],"QP-8":[143],"Our":[145],"work":[146],"demonstrates":[147],"average":[149],"2.51x,":[150],"5.72x,":[151],"4.37x":[153],"HP-16,":[157],"SP-32,":[158],"DP64,":[160],"respectively,":[161],"compared":[162],"related":[164],"works.":[165]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}