{"id":"https://openalex.org/W4413755403","doi":"https://doi.org/10.1109/isvlsi65124.2025.11130260","title":"ASIC Design Flow Using Simulink and Cadence Digital IC Design Tools","display_name":"ASIC Design Flow Using Simulink and Cadence Digital IC Design Tools","publication_year":2025,"publication_date":"2025-07-06","ids":{"openalex":"https://openalex.org/W4413755403","doi":"https://doi.org/10.1109/isvlsi65124.2025.11130260"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi65124.2025.11130260","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi65124.2025.11130260","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112508035","display_name":"CH.Bhaskar Rao","orcid":null},"institutions":[{"id":"https://openalex.org/I59897056","display_name":"California State University, Long Beach","ror":"https://ror.org/0080fxk18","country_code":"US","type":"education","lineage":["https://openalex.org/I59897056"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Charanya K Rao","raw_affiliation_strings":["California State University - Long Beach,Department of Electrical Engineering,Long Beach,USA"],"affiliations":[{"raw_affiliation_string":"California State University - Long Beach,Department of Electrical Engineering,Long Beach,USA","institution_ids":["https://openalex.org/I59897056"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5119450577","display_name":"Ashmitha Talluri","orcid":null},"institutions":[{"id":"https://openalex.org/I59897056","display_name":"California State University, Long Beach","ror":"https://ror.org/0080fxk18","country_code":"US","type":"education","lineage":["https://openalex.org/I59897056"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ashmitha Talluri","raw_affiliation_strings":["California State University - Long Beach,Department of Electrical Engineering,Long Beach,USA"],"affiliations":[{"raw_affiliation_string":"California State University - Long Beach,Department of Electrical Engineering,Long Beach,USA","institution_ids":["https://openalex.org/I59897056"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001971440","display_name":"Ava Hedayatipour","orcid":"https://orcid.org/0000-0003-1034-3616"},"institutions":[{"id":"https://openalex.org/I59897056","display_name":"California State University, Long Beach","ror":"https://ror.org/0080fxk18","country_code":"US","type":"education","lineage":["https://openalex.org/I59897056"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ava Hedayatipour","raw_affiliation_strings":["California State University - Long Beach,Department of Electrical Engineering,Long Beach,USA"],"affiliations":[{"raw_affiliation_string":"California State University - Long Beach,Department of Electrical Engineering,Long Beach,USA","institution_ids":["https://openalex.org/I59897056"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5112508035"],"corresponding_institution_ids":["https://openalex.org/I59897056"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.27103455,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9329000115394592,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9329000115394592,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11159","display_name":"Manufacturing Process and Optimization","score":0.9132000207901001,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cadence","display_name":"Cadence","score":0.9103351831436157},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.8351750373840332},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.7536405324935913},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.6357351541519165},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6240212321281433},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5711918473243713},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4115182161331177},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37797489762306213},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3734144866466522},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2470094859600067},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.22257602214813232}],"concepts":[{"id":"https://openalex.org/C2777125575","wikidata":"https://www.wikidata.org/wiki/Q14088448","display_name":"Cadence","level":2,"score":0.9103351831436157},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.8351750373840332},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.7536405324935913},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.6357351541519165},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6240212321281433},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5711918473243713},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4115182161331177},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37797489762306213},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3734144866466522},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2470094859600067},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.22257602214813232}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvlsi65124.2025.11130260","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi65124.2025.11130260","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W2743305891","https://openalex.org/W2126983197","https://openalex.org/W2070693700","https://openalex.org/W2078506771","https://openalex.org/W2908947570","https://openalex.org/W4391382037","https://openalex.org/W2374651972","https://openalex.org/W2098316714"],"abstract_inverted_index":{"The":[0,68,100],"complexity":[1],"of":[2,16,30,86,107],"modern":[3],"ASICs":[4],"has":[5],"increased":[6],"the":[7,14,20,28,48,54,74,82,87,95,135,144,171],"demand":[8],"for":[9,112,129,179],"efficient":[10],"methodologies":[11],"that":[12],"integrate":[13],"implementation":[15,29,132],"high-level":[17],"modeling":[18],"with":[19,65,73],"back-end":[21],"physical":[22,130],"layout":[23,156,195],"design.":[24,88],"This":[25,89,122,141],"integration":[26],"enables":[27],"complex":[31],"algorithms":[32],"as":[33,104],"systems":[34],"on":[35,165],"chip":[36,139],"(SoC).":[37],"In":[38],"this":[39,108],"work,":[40],"a":[41,60,66,105,166,183,193,197],"continuousstate":[42],"model":[43],"is":[44,71,91,110,126],"first":[45],"discretized":[46],"by":[47,53],"designer":[49],"and":[50,84,137,151,158,192],"then":[51,92,127],"digitized":[52],"Simulink":[55,154],"HDL":[56],"coder":[57],"to":[58,80,133,155],"extract":[59],"synthesizable":[61],"RTL":[62,69],"code":[63,70],"along":[64],"testbench.":[67],"simulated":[72],"test":[75],"bench":[76],"in":[77,94,153,160],"Cadence":[78,161],"Xcelium":[79],"verify":[81],"logic":[83,90],"functionality":[85],"synthesized":[93,123],"Genus":[96],"Stylus":[97],"UI":[98],"mode.":[99],"gate-level":[101],"netlist":[102],"produced":[103],"result":[106],"synthesis":[109],"used":[111],"digital":[113],"IC":[114],"design":[115,124,131,146,157],"using":[116,196],"45":[117],"nm":[118],"technology":[119],"library":[120],"files.":[121],"database":[125],"processed":[128],"obtain":[134],"DRC":[136],"LVS-clean":[138],"layout.":[140],"work":[142],"demonstrates":[143,174],"complete":[145],"flow,":[147],"from":[148],"frontend":[149],"definition":[150],"simulation":[152],"verification":[159],"tools.":[162],"Although":[163],"based":[164],"simple":[167],"3-bit":[168],"SISO":[169],"register,":[170],"proposed":[172],"methodology":[173],"an":[175],"efficient,":[176],"scalable":[177],"approach":[178],"ASIC":[180],"implementation,":[181],"achieving":[182],"$39.4":[184],"\\%$":[185],"total":[186],"power":[187],"reduction":[188],"through":[189],"clock":[190],"gating,":[191],"DRC/LVS-clean":[194],"unified":[198],"Simulink-Cadence":[199],"toolchain.":[200]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}