{"id":"https://openalex.org/W4413755577","doi":"https://doi.org/10.1109/isvlsi65124.2025.11130252","title":"Enabling fully connected probabilistic computing through a fast pipelined multi-operand adder","display_name":"Enabling fully connected probabilistic computing through a fast pipelined multi-operand adder","publication_year":2025,"publication_date":"2025-07-06","ids":{"openalex":"https://openalex.org/W4413755577","doi":"https://doi.org/10.1109/isvlsi65124.2025.11130252"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi65124.2025.11130252","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi65124.2025.11130252","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090519910","display_name":"G. Orlandi","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Giacomo Orlandi","raw_affiliation_strings":["Politecnico di Torino,Department of Electronics and Telecommunications,Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Department of Electronics and Telecommunications,Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086512343","display_name":"Christian Conti","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Christian Conti","raw_affiliation_strings":["Politecnico di Torino,Department of Electronics and Telecommunications,Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Department of Electronics and Telecommunications,Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012025330","display_name":"Marco Vacca","orcid":"https://orcid.org/0000-0003-2920-3357"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Vacca","raw_affiliation_strings":["Politecnico di Torino,Department of Electronics and Telecommunications,Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Department of Electronics and Telecommunications,Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036441962","display_name":"Mariagrazia Graziano","orcid":"https://orcid.org/0000-0002-8721-9990"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mariagrazia Graziano","raw_affiliation_strings":["Politecnico di Torino,Department of Applied Science and Technology,Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Department of Applied Science and Technology,Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009147665","display_name":"Fabrizio Riente","orcid":"https://orcid.org/0000-0003-4147-1098"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Fabrizio Riente","raw_affiliation_strings":["Politecnico di Torino,Department of Electronics and Telecommunications,Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Department of Electronics and Telecommunications,Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5090519910"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.30271084,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.953000009059906,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.953000009059906,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9526000022888184,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9510999917984009,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.8974728584289551},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8751349449157715},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7743446826934814},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6946373581886292},{"id":"https://openalex.org/keywords/probabilistic-logic","display_name":"Probabilistic logic","score":0.6542119979858398},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3376120626926422},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.13847211003303528},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10769021511077881}],"concepts":[{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.8974728584289551},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8751349449157715},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7743446826934814},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6946373581886292},{"id":"https://openalex.org/C49937458","wikidata":"https://www.wikidata.org/wiki/Q2599292","display_name":"Probabilistic logic","level":2,"score":0.6542119979858398},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3376120626926422},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.13847211003303528},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10769021511077881},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvlsi65124.2025.11130252","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi65124.2025.11130252","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1983849809","https://openalex.org/W2039122980","https://openalex.org/W2167036627","https://openalex.org/W2170171286","https://openalex.org/W2210692376","https://openalex.org/W2593865516","https://openalex.org/W2766775637","https://openalex.org/W2892017536","https://openalex.org/W2921525502","https://openalex.org/W2938847643","https://openalex.org/W2947189577","https://openalex.org/W3203392333","https://openalex.org/W4213210950","https://openalex.org/W4226006885","https://openalex.org/W4324290543","https://openalex.org/W4360596994","https://openalex.org/W4396929179","https://openalex.org/W4403510498","https://openalex.org/W4409132204"],"related_works":["https://openalex.org/W2556282987","https://openalex.org/W1533508804","https://openalex.org/W4390550886","https://openalex.org/W2050923821","https://openalex.org/W4285082868","https://openalex.org/W2072220574","https://openalex.org/W2162004439","https://openalex.org/W2558076308","https://openalex.org/W4317402486","https://openalex.org/W2120552212"],"abstract_inverted_index":{"Probabilistic":[0,14],"computing":[1,182],"has":[2],"gained":[3],"a":[4,55,60,65,77,99,110,121,173,188],"prominent":[5,111],"role":[6],"as":[7],"combinatorial":[8],"optimization":[9],"solvers":[10],"on":[11,39,162],"classical":[12],"hardware.":[13],"bits":[15],"(pbits)":[16],"must":[17],"be":[18],"updated":[19],"sequentially":[20],"to":[21,24,41,44,63,105,116],"rapidly":[22],"converge":[23],"the":[25,30,35,47,70,195],"lowest":[26],"energy":[27],"state":[28],"of":[29,69,113,197],"objective":[31],"function.":[32],"Yet,":[33],"all":[34,90],"current":[36],"implementations":[37,161],"rely":[38],"mappings":[40],"sparse":[42,106,163],"graphs":[43],"speed":[45],"up":[46],"update":[48,154],"operation.":[49],"In":[50],"this":[51,177],"paper,":[52],"we":[53],"present":[54],"new":[56,127],"pipelining":[57],"technique":[58],"for":[59,169,183],"multi-operand":[61],"adder":[62,101,124],"enable":[64,179],"fully":[66,184],"connected":[67,92,185],"structure":[68],"pbit":[71,87],"native":[72],"graph.":[73],"Previous":[74],"approaches":[75],"lack":[76],"pipelined":[78,123,139],"architecture":[79],"and":[80,108,147],"avoid":[81],"data":[82,134],"dependencies":[83,135],"by":[84],"updating":[85],"each":[86,130],"only":[88],"after":[89],"its":[91],"pbits":[93,114,153],"are":[94],"updated.":[95],"This":[96],"results":[97],"in":[98,194],"small":[100],"but":[102],"limits":[103],"execution":[104],"problems":[107],"implies":[109],"supplement":[112],"due":[115],"sparsification.":[117],"Our":[118],"implementation":[119],"uses":[120],"fast":[122,180],"that":[125],"receives":[126],"operands":[128],"at":[129],"pipe":[131],"stage,":[132],"handling":[133],"during":[136],"execution.":[137],"The":[138,156],"unit":[140],"was":[141],"evaluated":[142],"against":[143],"other":[144],"pipeline":[145],"strategies":[146],"state-of-the-art":[148],"emulator":[149],"implementations,":[150],"demonstrating":[151],"promising":[152],"times.":[155],"obtained":[157],"performance":[158],"closely":[159],"matches":[160],"graphs,":[164],"implying":[165],"greater":[166],"scalability,":[167],"especially":[168],"denser":[170],"problems.":[171],"With":[172],"future":[174],"parallelized":[175],"architecture,":[176],"may":[178],"probabilistic":[181],"problems,":[186],"avoiding":[187],"significant":[189],"or":[190],"even":[191],"unacceptable":[192],"increase":[193],"number":[196],"required":[198],"pbits.":[199]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}