{"id":"https://openalex.org/W4413755432","doi":"https://doi.org/10.1109/isvlsi65124.2025.11130239","title":"Efficient Logic Evaluation Using RRAM-Based In-Memory Computing","display_name":"Efficient Logic Evaluation Using RRAM-Based In-Memory Computing","publication_year":2025,"publication_date":"2025-07-06","ids":{"openalex":"https://openalex.org/W4413755432","doi":"https://doi.org/10.1109/isvlsi65124.2025.11130239"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi65124.2025.11130239","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi65124.2025.11130239","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027492960","display_name":"Shuhang Zhang","orcid":"https://orcid.org/0000-0003-1313-2726"},"institutions":[{"id":"https://openalex.org/I4210140450","display_name":"Infineon Technologies (Canada)","ror":"https://ror.org/04hbev594","country_code":"CA","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210140450"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Shuhang Zhang","raw_affiliation_strings":["Infineon Technologies AG"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG","institution_ids":["https://openalex.org/I4210140450"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5027492960"],"corresponding_institution_ids":["https://openalex.org/I4210140450"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.27247401,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.7397631406784058},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7160921692848206},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4391816556453705},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3272625207901001},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2577763795852661},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14359626173973083},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10142585635185242},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07103031873703003}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.7397631406784058},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7160921692848206},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4391816556453705},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3272625207901001},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2577763795852661},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14359626173973083},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10142585635185242},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07103031873703003}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvlsi65124.2025.11130239","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi65124.2025.11130239","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5099999904632568}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2020622255","https://openalex.org/W2065076119","https://openalex.org/W4384616198","https://openalex.org/W2054635671","https://openalex.org/W4312727691","https://openalex.org/W2588373136","https://openalex.org/W2791102142","https://openalex.org/W4405522369","https://openalex.org/W2088897617","https://openalex.org/W2526337279"],"abstract_inverted_index":{"In":[0,100],"recent":[1],"years,":[2],"in-memory":[3,67,108],"computing":[4,62,68,109,145,168,181],"has":[5],"been":[6,24],"extensively":[7],"utilized":[8],"for":[9,26,50,76,139,177,198],"data-intensive":[10],"applications":[11],"due":[12,35],"to":[13,36,39,82,112,157,202],"its":[14,37],"high":[15,83],"speed":[16],"and":[17,85,130],"energy":[18,86],"efficiency.":[19,99,150,161],"Various":[20],"memory":[21],"technologies":[22],"have":[23],"explored":[25],"this":[27,101],"purpose,":[28],"with":[29],"Resistive":[30],"Memory":[31],"(RRAM)":[32],"standing":[33],"out":[34],"ability":[38],"naturally":[40],"implement":[41],"MultiplyAccumulate":[42],"(MAC)":[43],"operations,":[44,79],"making":[45],"it":[46,184],"a":[47,105,195],"promising":[48],"solution":[49],"neural":[51],"network":[52],"acceleration.":[53],"Additionally,":[54,151],"RRAM":[55],"is":[56],"also":[57],"applied":[58],"in":[59,191],"general":[60],"logic":[61,66,107,121,172,199],"applications.":[63],"However,":[64],"RRAM-based":[65],"faces":[69],"notable":[70],"challenges,":[71],"such":[72],"as":[73],"the":[74,120,137,144,175,180,192],"need":[75,176],"repeated":[77],"write":[78,141],"which":[80],"leads":[81],"latency":[84],"inefficiency.":[87],"Furthermore,":[88,183],"synthesized":[89],"circuits":[90],"often":[91],"require":[92],"mapping":[93],"into":[94,127],"large":[95],"crossbars,":[96],"reducing":[97],"area":[98,160],"work,":[102],"we":[103,152],"introduce":[104],"novel":[106],"framework":[110,118,169],"designed":[111],"address":[113],"these":[114],"issues.":[115],"Our":[116],"proposed":[117,167],"transforms":[119],"evaluation":[122,173],"of":[123,189],"AndInverter":[124],"Graphs":[125],"(AIGs)":[126],"MAC":[128],"operations":[129,142],"binary":[131],"step":[132],"functions.":[133],"This":[134],"method":[135],"eliminates":[136],"necessity":[138],"frequent":[140],"during":[143,179],"phase,":[146],"thereby":[147],"enhancing":[148],"operational":[149],"propose":[153],"two":[154],"optimization":[155],"techniques":[156],"achieve":[158],"better":[159],"Simulation":[162],"results":[163],"demonstrate":[164],"that":[165],"our":[166],"can":[170],"perform":[171],"without":[174],"writing":[178],"phase.":[182],"achieves":[185],"an":[186],"average":[187],"reduction":[188],"86.13%":[190],"Area-Latency-Product":[193],"(ALP),":[194],"key":[196],"metric":[197],"evaluation,":[200],"compared":[201],"traditional":[203],"designs.":[204]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}