{"id":"https://openalex.org/W4386474847","doi":"https://doi.org/10.1109/isvlsi59464.2023.10238642","title":"Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis","display_name":"Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis","publication_year":2023,"publication_date":"2023-06-20","ids":{"openalex":"https://openalex.org/W4386474847","doi":"https://doi.org/10.1109/isvlsi59464.2023.10238642"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi59464.2023.10238642","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/isvlsi59464.2023.10238642","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011952896","display_name":"Gabriel Ammes","orcid":"https://orcid.org/0000-0002-3929-4427"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Gabriel Ammes","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS),PPGC,Porto Alegre,Brazil","PPGC, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS),PPGC,Porto Alegre,Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"PPGC, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062131940","display_name":"Paulo F. Butzen","orcid":"https://orcid.org/0000-0003-1587-7596"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Paulo F. Butzen","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS),PGMICRO,Porto Alegre,Brazil","PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS),PGMICRO,Porto Alegre,Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Andr\u00e9 I. Reis","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS),PPGC,Porto Alegre,Brazil","PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","PPGC, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS),PPGC,Porto Alegre,Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"PPGC, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Renato P. Ribas","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS),PGMICRO,Porto Alegre,Brazil","PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS),PGMICRO,Porto Alegre,Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.684669554233551},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5711845755577087},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5636835694313049},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5487093925476074},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5153164863586426},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49952006340026855},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4858526885509491},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.47029539942741394},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.4352443218231201},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.4225970208644867},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3926756680011749},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37779104709625244},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.36485135555267334},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3470122814178467},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21122118830680847},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.19418540596961975},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12483444809913635},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10645726323127747},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.09907341003417969}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.684669554233551},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5711845755577087},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5636835694313049},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5487093925476074},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5153164863586426},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49952006340026855},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4858526885509491},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.47029539942741394},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4352443218231201},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.4225970208644867},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3926756680011749},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37779104709625244},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.36485135555267334},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3470122814178467},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21122118830680847},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.19418540596961975},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12483444809913635},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10645726323127747},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.09907341003417969},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvlsi59464.2023.10238642","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/isvlsi59464.2023.10238642","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8500000238418579}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321091","display_name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","ror":"https://ror.org/00x0ma614"},{"id":"https://openalex.org/F4320322025","display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","ror":"https://ror.org/03swz6y49"},{"id":"https://openalex.org/F4320322502","display_name":"Funda\u00e7\u00e3o de Amparo \u00e0 Pesquisa do Estado do Rio Grande do Sul","ror":"https://ror.org/05k49za97"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W2100465945","https://openalex.org/W2105761964","https://openalex.org/W2129183345","https://openalex.org/W2244005500","https://openalex.org/W2265166184","https://openalex.org/W2346205343","https://openalex.org/W2612139336","https://openalex.org/W2728756936","https://openalex.org/W2900271492","https://openalex.org/W2908171364","https://openalex.org/W2980513533","https://openalex.org/W2996685260","https://openalex.org/W3036459403","https://openalex.org/W3071517735","https://openalex.org/W3092498068","https://openalex.org/W3128695338","https://openalex.org/W3186831878","https://openalex.org/W3214138519","https://openalex.org/W3215215428","https://openalex.org/W4255029913","https://openalex.org/W4280584399","https://openalex.org/W4293053810","https://openalex.org/W4318224782"],"related_works":["https://openalex.org/W4386159957","https://openalex.org/W2373127312","https://openalex.org/W4241206086","https://openalex.org/W2386022279","https://openalex.org/W659242671","https://openalex.org/W2351310008","https://openalex.org/W2181841040","https://openalex.org/W2377041390","https://openalex.org/W2913530739","https://openalex.org/W2152365648"],"abstract_inverted_index":{"Approximate":[0],"circuits":[1],"are":[2],"emerging":[3],"as":[4,18],"an":[5,29],"alternative":[6],"to":[7,90,104,111],"save":[8],"area,":[9],"delay,":[10],"and":[11,23,39,77,86,109],"power":[12],"consumption":[13],"in":[14,42,82,106,113],"error-resilient":[15],"applications":[16],"such":[17,48],"machine":[19],"learning,":[20],"computer":[21],"vision,":[22],"signal":[24],"processing.":[25],"This":[26],"work":[27],"presents":[28],"evaluation":[30],"of":[31,72,75,96,102],"a":[32,49,100],"logic":[33,54],"synthesis":[34,55],"approach":[35],"by":[36],"exploring":[37],"two-":[38],"multi-level":[40,62],"topologies":[41],"approximating":[43],"digital":[44],"circuit":[45,107],"design.":[46],"In":[47],"strategy,":[50],"two-level":[51],"(2L)":[52],"approximated":[53],"(ALS)":[56],"unlocks":[57],"robust":[58],"function":[59],"optimization,":[60],"whereas":[61],"(ML)":[63],"ALS":[64],"acts":[65],"over":[66],"the":[67,83,91,116],"structure":[68],"simplification.":[69],"Experimental":[70],"results":[71],"combined":[73],"exploitation":[74],"2L-":[76],"ML-ALS":[78,93],"have":[79],"shown":[80],"improvement":[81],"average":[84],"area":[85,108],"delay":[87,114],"optimization":[88],"compared":[89],"state-of-the-art":[92],"for":[94,115],"5%":[95],"error":[97,118],"rate,":[98],"being":[99],"reduction":[101],"up":[103,110],"37%":[105],"31%":[112],"same":[117],"constraint.":[119]},"counts_by_year":[],"updated_date":"2026-07-25T15:57:00.446498","created_date":"2025-10-10T00:00:00"}
