{"id":"https://openalex.org/W4386486848","doi":"https://doi.org/10.1109/isvlsi59464.2023.10238626","title":"Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs","display_name":"Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs","publication_year":2023,"publication_date":"2023-06-20","ids":{"openalex":"https://openalex.org/W4386486848","doi":"https://doi.org/10.1109/isvlsi59464.2023.10238626"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi59464.2023.10238626","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi59464.2023.10238626","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112680183","display_name":"Grant Brown","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Grant Brown","raw_affiliation_strings":["University of Utah"],"affiliations":[{"raw_affiliation_string":"University of Utah","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006420890","display_name":"Ganesh Gore","orcid":"https://orcid.org/0000-0002-0310-197X"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ganesh Gore","raw_affiliation_strings":["University of Utah"],"affiliations":[{"raw_affiliation_string":"University of Utah","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002568331","display_name":"Pierre\u2010Emmanuel Gaillardon","orcid":"https://orcid.org/0000-0003-3634-3999"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pierre-Emmanuel Gaillardon","raw_affiliation_strings":["University of Utah"],"affiliations":[{"raw_affiliation_string":"University of Utah","institution_ids":["https://openalex.org/I223532165"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5112680183"],"corresponding_institution_ids":["https://openalex.org/I223532165"],"apc_list":null,"apc_paid":null,"fwci":0.4021,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.60369927,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7656036615371704},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7453042268753052},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5576528906822205},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.45592573285102844},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.45004802942276},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.4319995045661926},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.430133581161499},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.41253384947776794},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34767186641693115},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3443508744239807},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.22643816471099854}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7656036615371704},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7453042268753052},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5576528906822205},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.45592573285102844},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.45004802942276},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.4319995045661926},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.430133581161499},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.41253384947776794},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34767186641693115},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3443508744239807},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.22643816471099854},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvlsi59464.2023.10238626","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi59464.2023.10238626","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4000000059604645}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1669114967","https://openalex.org/W1963807856","https://openalex.org/W1973183555","https://openalex.org/W2000606381","https://openalex.org/W2062395080","https://openalex.org/W2086497127","https://openalex.org/W2094440989","https://openalex.org/W2113289989","https://openalex.org/W2136768070","https://openalex.org/W2160252016","https://openalex.org/W2162756981","https://openalex.org/W2167220336","https://openalex.org/W2949216549","https://openalex.org/W2988212920","https://openalex.org/W3136031055","https://openalex.org/W4250702245","https://openalex.org/W6637097397","https://openalex.org/W6679965590","https://openalex.org/W6684120545","https://openalex.org/W6684549007","https://openalex.org/W6791995632"],"related_works":["https://openalex.org/W2164834710","https://openalex.org/W4232019485","https://openalex.org/W2028052815","https://openalex.org/W4327499872","https://openalex.org/W2123512677","https://openalex.org/W2116259070","https://openalex.org/W2165367082","https://openalex.org/W2128528443","https://openalex.org/W2132668926","https://openalex.org/W2070693700"],"abstract_inverted_index":{"Field":[0],"Programmable":[1],"Gate":[2],"Arrays":[3],"(FPGA)":[4],"have":[5,44,56,86],"grown":[6],"in":[7,9,89,198,205],"popularity":[8],"a":[10,95,139,146,195,202],"myriad":[11],"of":[12,98,120],"applications":[13],"due":[14],"to":[15,25,60,74,150,166,194,209],"their":[16],"reconfigurablity":[17],"and":[18,38,100,181,200],"lower":[19],"non-recurrent":[20],"engineering":[21],"costs":[22],"when":[23,207],"compared":[24,208],"application":[26,36,63],"specific":[27],"integrated":[28],"circuits":[29],"(ASIC).":[30],"To":[31,133],"keep":[32],"pace":[33],"with":[34],"growing":[35],"needs":[37],"process":[39],"technology":[40],"improvements,":[41],"commerical":[42],"FPGAs":[43,54,184],"traditionally":[45],"chosen":[46],"full":[47],"custom":[48],"chip":[49],"design":[50,72,78,84,91,107,115],"approaches.":[51],"However,":[52],"embedded":[53],"(eFPGA)":[55],"redesigned":[57],"FPGA":[58,83,130],"uses":[59],"be":[61],"more":[62],"specific,":[64],"thereby":[65],"producing":[66],"the":[67,76,90,105,118],"need":[68],"for":[69,94,110],"an":[70,156,210],"agile":[71,82],"approach":[73],"accelerate":[75],"eFPGA":[77],"process.":[79],"Hence,":[80],"recent":[81],"methods":[85,116],"introduced":[87],"automation":[88],"process,":[92],"allowing":[93],"semi-automated":[96],"fine-tuning":[97],"physical":[99,106],"architectural":[101],"parameters":[102],"which":[103],"reduces":[104],"iteration":[108],"time":[109],"FPGAs.":[111],"The":[112],"novel":[113,140],"grid-based":[114],"render":[117],"usage":[119],"commercially":[121],"available":[122],"Clock":[123],"Tree":[124],"Synthesis":[125],"(CTS)":[126],"algorithms":[127],"on":[128,172],"modern":[129],"fabrics":[131],"ineffective.":[132],"overcome":[134],"these":[135],"deficiencies,":[136],"we":[137],"propose":[138],"clock":[141,148,168],"tree":[142,149],"embedding":[143],"algorithm,":[144],"utilizing":[145],"symmetrical":[147],"ensure":[151],"skew":[152,206],"minimization":[153],"followed":[154],"by":[155],"efficient":[157],"pruning":[158],"method":[159],"leveraging":[160],"traditional":[161],"Static":[162],"Timing":[163],"Analysis":[164],"(STA)":[165],"improve":[167],"latency.":[169],"Experimental":[170],"results":[171],"$2\\times":[173],"2,\\":[174],"7\\times":[175],"7,\\":[176],"8\\times":[177],"8,\\":[178],"29\\times":[179],"29$,":[180],"$32\\times":[182],"32$":[183],"show":[185],"that":[186],"our":[187],"proposed":[188],"CTS":[189,214],"algorithm":[190],"can":[191],"achieve":[192],"up":[193],"50%":[196],"improvement":[197],"latency":[199],"over":[201],"$10\\times$":[203],"reduction":[204],"implementation":[211],"using":[212],"commercial":[213],"methodology.":[215]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}