{"id":"https://openalex.org/W2738385198","doi":"https://doi.org/10.1109/isvlsi.2017.81","title":"Memristor-Based Clock Design and Optimization with In-Situ Tunability","display_name":"Memristor-Based Clock Design and Optimization with In-Situ Tunability","publication_year":2017,"publication_date":"2017-07-01","ids":{"openalex":"https://openalex.org/W2738385198","doi":"https://doi.org/10.1109/isvlsi.2017.81","mag":"2738385198"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi.2017.81","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2017.81","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084807334","display_name":"Shuyu Kong","orcid":"https://orcid.org/0000-0003-0782-6852"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shuyu Kong","raw_affiliation_strings":["EECS Department, Northwestern University, Evanston, IL, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"EECS Department, Northwestern University, Evanston, IL, U.S.A","institution_ids":["https://openalex.org/I111979921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005991726","display_name":"Jie Gu","orcid":"https://orcid.org/0000-0003-2912-7294"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jie Gu","raw_affiliation_strings":["EECS Department, Northwestern University, Evanston, IL, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"EECS Department, Northwestern University, Evanston, IL, U.S.A","institution_ids":["https://openalex.org/I111979921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103038285","display_name":"Hai Zhou","orcid":"https://orcid.org/0000-0003-4824-7179"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hai Zhou","raw_affiliation_strings":["EECS Department, Northwestern University, Evanston, IL, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"EECS Department, Northwestern University, Evanston, IL, U.S.A","institution_ids":["https://openalex.org/I111979921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I111979921"],"apc_list":null,"apc_paid":null,"fwci":0.3792,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.47085067,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"427","last_page":"432"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.7274446487426758},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.7261604070663452},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6862877011299133},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.647890031337738},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5786574482917786},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.5485310554504395},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47663769125938416},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.46861252188682556},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.44443103671073914},{"id":"https://openalex.org/keywords/millisecond","display_name":"Millisecond","score":0.42618703842163086},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.42116886377334595},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.41992810368537903},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36914294958114624},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1696341335773468},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.16650620102882385},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1412772536277771},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.11779195070266724}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.7274446487426758},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.7261604070663452},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6862877011299133},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.647890031337738},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5786574482917786},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.5485310554504395},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47663769125938416},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.46861252188682556},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.44443103671073914},{"id":"https://openalex.org/C60327585","wikidata":"https://www.wikidata.org/wiki/Q723733","display_name":"Millisecond","level":2,"score":0.42618703842163086},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.42116886377334595},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.41992810368537903},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36914294958114624},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1696341335773468},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.16650620102882385},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1412772536277771},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.11779195070266724},{"id":"https://openalex.org/C1276947","wikidata":"https://www.wikidata.org/wiki/Q333","display_name":"Astronomy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvlsi.2017.81","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2017.81","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1534348635","https://openalex.org/W1558331362","https://openalex.org/W1966741973","https://openalex.org/W2015148655","https://openalex.org/W2031600721","https://openalex.org/W2119211217","https://openalex.org/W2149864516","https://openalex.org/W2158750015","https://openalex.org/W2162651880","https://openalex.org/W2163031927","https://openalex.org/W2178304595","https://openalex.org/W4236324780","https://openalex.org/W4243059613","https://openalex.org/W4255469943","https://openalex.org/W6633599133","https://openalex.org/W6682236896"],"related_works":["https://openalex.org/W2116514610","https://openalex.org/W2003180247","https://openalex.org/W3201048403","https://openalex.org/W2144282137","https://openalex.org/W2891365107","https://openalex.org/W2032549010","https://openalex.org/W2391115906","https://openalex.org/W2098440959","https://openalex.org/W2138768308","https://openalex.org/W4386159819"],"abstract_inverted_index":{"Process":[0],"variation":[1],"is":[2],"the":[3,45,48,62,68,73,76,88,93,109],"dominating":[4],"factor":[5],"for":[6],"performance":[7,21],"degradation":[8],"in":[9,119],"modern":[10],"IC":[11],"chips.":[12],"The":[13],"conventional":[14],"guard-band":[15],"design":[16],"methodology":[17],"leads":[18],"to":[19,36,66,91,113],"significant":[20],"penalty.":[22],"This":[23],"paper":[24],"utilizes":[25],"an":[26,83],"emerging":[27],"non-volatile":[28],"resistive":[29],"device,":[30],"memristor,":[31],"with":[32,115],"timing":[33,42,69],"violation":[34,43],"detectors":[35],"dynamically":[37],"achieve":[38],"local":[39],"recovery":[40],"from":[41,111],"during":[44],"runtime,":[46],"eliminating":[47],"necessity":[49],"of":[50,75],"testing":[51],"phase.":[52],"It":[53,80],"develops":[54],"a":[55],"systematic":[56],"self-tuning":[57],"mechanism":[58],"that":[59,104],"globally":[60],"adjusts":[61],"clock":[63,89],"skew":[64],"scheduling":[65],"compensate":[67],"violation,":[70],"and":[71,98],"determines":[72],"tunability":[74],"memristor-based":[77],"self-tunable":[78],"circuits.":[79],"also":[81],"proposes":[82],"algorithmic":[84],"memristor":[85],"placement":[86],"across":[87],"tree":[90],"balance":[92],"tradeoff":[94],"between":[95],"hardware":[96],"cost":[97],"system":[99],"tunability.":[100],"Experimental":[101],"results":[102],"show":[103],"our":[105],"approach":[106],"can":[107],"improve":[108],"yield":[110],"90%":[112],"98%":[114],"only":[116],"4%":[117],"overhead":[118],"average.":[120]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
