{"id":"https://openalex.org/W2014218702","doi":"https://doi.org/10.1109/isvlsi.2013.6654630","title":"On-chip clock error characterization for clock distribution system","display_name":"On-chip clock error characterization for clock distribution system","publication_year":2013,"publication_date":"2013-08-01","ids":{"openalex":"https://openalex.org/W2014218702","doi":"https://doi.org/10.1109/isvlsi.2013.6654630","mag":"2014218702"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi.2013.6654630","is_oa":true,"landing_page_url":"https://doi.org/10.1109/isvlsi.2013.6654630","pdf_url":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6654630","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6654630","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100898555","display_name":"Chuan Shan","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"LIP6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Chuan Shan","raw_affiliation_strings":["Laboratoire d'informatique de Paris 6 (LIP6), Universit\u00e9 Pierre& Marie Curie (UPMC), Paris, France","Lab. d'Inf. de Paris 6 (LIP6), Univ. Pierre & Marie Curie (UPMC), Paris, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratoire d'informatique de Paris 6 (LIP6), Universit\u00e9 Pierre& Marie Curie (UPMC), Paris, France","institution_ids":["https://openalex.org/I39804081","https://openalex.org/I4210159731"]},{"raw_affiliation_string":"Lab. d'Inf. de Paris 6 (LIP6), Univ. Pierre & Marie Curie (UPMC), Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032777255","display_name":"Dimitri Galayko","orcid":"https://orcid.org/0000-0002-7056-7489"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"LIP6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Dimitri Galayko","raw_affiliation_strings":["Laboratoire d'informatique de Paris 6 (LIP6), Universit\u00e9 Pierre& Marie Curie (UPMC), Paris, France","Lab. d'Inf. de Paris 6 (LIP6), Univ. Pierre & Marie Curie (UPMC), Paris, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratoire d'informatique de Paris 6 (LIP6), Universit\u00e9 Pierre& Marie Curie (UPMC), Paris, France","institution_ids":["https://openalex.org/I39804081","https://openalex.org/I4210159731"]},{"raw_affiliation_string":"Lab. d'Inf. de Paris 6 (LIP6), Univ. Pierre & Marie Curie (UPMC), Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112858873","display_name":"Fran\u00e7ois Anceau","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"LIP6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Francois Anceau","raw_affiliation_strings":["Laboratoire d'informatique de Paris 6 (LIP6), Universit\u00e9 Pierre& Marie Curie (UPMC), Paris, France","Lab. d'Inf. de Paris 6 (LIP6), Univ. Pierre & Marie Curie (UPMC), Paris, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratoire d'informatique de Paris 6 (LIP6), Universit\u00e9 Pierre& Marie Curie (UPMC), Paris, France","institution_ids":["https://openalex.org/I39804081","https://openalex.org/I4210159731"]},{"raw_affiliation_string":"Lab. d'Inf. de Paris 6 (LIP6), Univ. Pierre & Marie Curie (UPMC), Paris, France","institution_ids":["https://openalex.org/I39804081"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4053,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.51350185,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"102","last_page":"108"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6912791728973389},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6577243804931641},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5848392844200134},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5778573751449585},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.561716616153717},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4560636281967163},{"id":"https://openalex.org/keywords/characterization","display_name":"Characterization (materials science)","score":0.4210735559463501},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13873744010925293},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11572393774986267},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.09683117270469666},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09646603465080261}],"concepts":[{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6912791728973389},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6577243804931641},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5848392844200134},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5778573751449585},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.561716616153717},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4560636281967163},{"id":"https://openalex.org/C2780841128","wikidata":"https://www.wikidata.org/wiki/Q5073781","display_name":"Characterization (materials science)","level":2,"score":0.4210735559463501},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13873744010925293},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11572393774986267},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.09683117270469666},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09646603465080261},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/isvlsi.2013.6654630","is_oa":true,"landing_page_url":"https://doi.org/10.1109/isvlsi.2013.6654630","pdf_url":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6654630","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-01053759v1","is_oa":true,"landing_page_url":"https://hal.sorbonne-universite.fr/hal-01053759","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on, Aug 2013, Natal, Brazil. pp.102-108, ⟨10.1109/ISVLSI.2013.6654630⟩","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"doi:10.1109/isvlsi.2013.6654630","is_oa":true,"landing_page_url":"https://doi.org/10.1109/isvlsi.2013.6654630","pdf_url":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6654630","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1870817321","https://openalex.org/W1979163729","https://openalex.org/W1992376115","https://openalex.org/W2036460278","https://openalex.org/W2037306258","https://openalex.org/W2062952706","https://openalex.org/W2096486545","https://openalex.org/W2117966934","https://openalex.org/W2118232269","https://openalex.org/W2126936678","https://openalex.org/W2135663303","https://openalex.org/W2169790941"],"related_works":["https://openalex.org/W2362169398","https://openalex.org/W2147289961","https://openalex.org/W2139353707","https://openalex.org/W3083915265","https://openalex.org/W2285671215","https://openalex.org/W2056395150","https://openalex.org/W2031867410","https://openalex.org/W2071924372","https://openalex.org/W2048949011","https://openalex.org/W4232271862"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"investigate":[4],"a":[5,46,90,98,113],"test":[6],"strategy":[7,76],"for":[8],"characterization":[9],"of":[10,37,45,65,116,138],"clock":[11,16,38],"error":[12,39],"statistics":[13],"between":[14,50],"two":[15,51,139],"domains":[17],"in":[18],"high-speed":[19],"clocking":[20,52],"systems":[21],"(gigahertz":[22],"and":[23,62,96,130,135],"more).":[24],"The":[25,54,75,84,121],"method":[26,55],"allows":[27],"an":[28],"indirect":[29],"measurement":[30,114],"(not":[31],"based":[32],"on":[33],"time":[34],"interval":[35],"measurement)":[36],"distribution":[40],"by":[41,89],"observing":[42],"the":[43,63,124,127,132],"integrity":[44],"periodic":[47],"sequence":[48],"transmitted":[49],"domains.":[53],"is":[56,70],"compatible":[57],"with":[58],"fully":[59],"on-chip":[60,101],"implementation,":[61,129],"readout":[64],"result":[66],"to":[67],"off-chip":[68],"signals":[69],"cadenced":[71],"at":[72,78,93],"low":[73],"rate.":[74],"aims":[77],"picoseconds":[79],"resolution":[80],"without":[81],"complex":[82],"calibration.":[83],"idea":[85],"was":[86,103],"first":[87],"validated":[88],"discrete":[91],"prototype":[92,102],"downscaled":[94],"frequencies,":[95],"then":[97],"high":[99],"frequency":[100],"designed":[104],"using":[105],"65":[106],"nm":[107],"CMOS":[108],"technology.":[109],"Simulation":[110],"results":[111,137],"predict":[112],"precision":[115],"less":[117],"than":[118],"\u00b12.5":[119],"ps.":[120],"article":[122],"presents":[123],"theory,":[125],"exposes":[126],"hardware":[128],"reports":[131],"experimental":[133],"validation":[134],"simulation":[136],"prototypes.":[140]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}