{"id":"https://openalex.org/W2120496642","doi":"https://doi.org/10.1109/isvlsi.2004.1339554","title":"A subworld-parallel multiplication and sum-of-squares unit","display_name":"A subworld-parallel multiplication and sum-of-squares unit","publication_year":2004,"publication_date":"2004-10-04","ids":{"openalex":"https://openalex.org/W2120496642","doi":"https://doi.org/10.1109/isvlsi.2004.1339554","mag":"2120496642"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi.2004.1339554","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2004.1339554","pdf_url":null,"source":{"id":"https://openalex.org/S4306418593","display_name":"IEEE Computer Society Annual Symposium on VLSI","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062047506","display_name":"S. Krithivasan","orcid":null},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Krithivasan","raw_affiliation_strings":["University of Wisconsin, Madison, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wisconsin, Madison, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084396956","display_name":"M.J. Schulte","orcid":null},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.J. Schulte","raw_affiliation_strings":["University of Wisconsin, Madison, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wisconsin, Madison, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086798411","display_name":"John Glossner","orcid":"https://orcid.org/0000-0003-0713-2105"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J. Glossner","raw_affiliation_strings":["Sandbridge Technologies, Inc., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sandbridge Technologies, Inc., USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.241,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.78588991,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"273","last_page":"274"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.9300609827041626},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7581612467765808},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6989133358001709},{"id":"https://openalex.org/keywords/multiplication","display_name":"Multiplication (music)","score":0.6936067342758179},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.6058775782585144},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.5574281811714172},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.5075777769088745},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.48294657468795776},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3299192190170288},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.17755168676376343},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1253725290298462}],"concepts":[{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.9300609827041626},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7581612467765808},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6989133358001709},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.6936067342758179},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.6058775782585144},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5574281811714172},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.5075777769088745},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.48294657468795776},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3299192190170288},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17755168676376343},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1253725290298462},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvlsi.2004.1339554","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2004.1339554","pdf_url":null,"source":{"id":"https://openalex.org/S4306418593","display_name":"IEEE Computer Society Annual Symposium on VLSI","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1504490355","https://openalex.org/W2114366942","https://openalex.org/W2163894825","https://openalex.org/W2170588228"],"related_works":["https://openalex.org/W2967107136","https://openalex.org/W2072220574","https://openalex.org/W4285082868","https://openalex.org/W2089343558","https://openalex.org/W2558076308","https://openalex.org/W2162004439","https://openalex.org/W4317402486","https://openalex.org/W2120552212","https://openalex.org/W2015084332","https://openalex.org/W2081051399"],"abstract_inverted_index":{"Several":[0],"recent":[1],"digital":[2],"signal":[3],"processors,":[4,6],"multimedia":[5,11],"and":[7,53,63,91],"general-purpose":[8],"processors":[9],"with":[10,89],"extensions":[12],"support":[13],"subword":[14,17,61],"parallelism.":[15],"With":[16],"parallelism,":[18],"each":[19],"operand":[20],"is":[21],"partitioned":[22],"into":[23],"multiple":[24,38],"lower-precision":[25],"operands,":[26],"called":[27],"subwords.":[28],"A":[29],"single":[30],"subword-parallel":[31,51,87],"instruction":[32],"performs":[33,86],"the":[34,47],"same":[35],"operation":[36],"on":[37],"sets":[39],"of":[40,49,99],"subwords":[41],"in":[42,81],"parallel.":[43,82],"This":[44],"paper":[45],"presents":[46],"design":[48],"a":[50,100],"multiplication":[52],"sum-of-squares":[54,79],"unit":[55],"(SPMSSU).":[56],"The":[57,83],"SPMSSU":[58,84],"uses":[59],"novel":[60],"partitioning":[62],"partial":[64],"product":[65],"mapping":[66],"techniques":[67],"to":[68,97],"perform":[69],"one":[70],"32-bit,":[71],"two":[72],"16-bit,":[73],"or":[74,78],"four":[75],"8-bit":[76],"multiplications":[77],"operations":[80,88],"efficiently":[85],"area":[90],"delay":[92],"estimates":[93],"that":[94],"are":[95],"comparable":[96],"those":[98],"conventional":[101],"32-bit":[102],"multiplier.":[103]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
