{"id":"https://openalex.org/W2163924241","doi":"https://doi.org/10.1109/isvlsi.2004.1339528","title":"Control and data flow graph extraction for high-level synthesis","display_name":"Control and data flow graph extraction for high-level synthesis","publication_year":2004,"publication_date":"2004-10-04","ids":{"openalex":"https://openalex.org/W2163924241","doi":"https://doi.org/10.1109/isvlsi.2004.1339528","mag":"2163924241"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi.2004.1339528","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2004.1339528","pdf_url":null,"source":{"id":"https://openalex.org/S4306418593","display_name":"IEEE Computer Society Annual Symposium on VLSI","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://stars.library.ucf.edu/scopus2000/5011","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007159072","display_name":"R.K. Namballa","orcid":null},"institutions":[{"id":"https://openalex.org/I2613432","display_name":"University of South Florida","ror":"https://ror.org/032db5x82","country_code":"US","type":"education","lineage":["https://openalex.org/I2613432"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Namballa","raw_affiliation_strings":["Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA","institution_ids":["https://openalex.org/I2613432"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027665366","display_name":"N. Ranganathan","orcid":null},"institutions":[{"id":"https://openalex.org/I2613432","display_name":"University of South Florida","ror":"https://ror.org/032db5x82","country_code":"US","type":"education","lineage":["https://openalex.org/I2613432"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N. Ranganathan","raw_affiliation_strings":["Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA","institution_ids":["https://openalex.org/I2613432"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063189795","display_name":"Abdel Ejnioui","orcid":null},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Ejnioui","raw_affiliation_strings":["Department of Computer Engineering, University of Central Florida, Orlando, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of Central Florida, Orlando, FL, USA","institution_ids":["https://openalex.org/I106165777"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.618,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.63676831,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"187","last_page":"192"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8250630497932434},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8129292726516724},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5953540205955505},{"id":"https://openalex.org/keywords/control-flow","display_name":"Control flow","score":0.579880952835083},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5578871369361877},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5271196961402893},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5053721070289612},{"id":"https://openalex.org/keywords/control-flow-graph","display_name":"Control flow graph","score":0.49374255537986755},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.484957218170166},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46789705753326416},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4599645733833313},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4466245770454407},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4280354082584381},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3146573305130005},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.27259963750839233},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2555949091911316}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8250630497932434},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8129292726516724},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5953540205955505},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.579880952835083},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5578871369361877},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5271196961402893},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5053721070289612},{"id":"https://openalex.org/C27458966","wikidata":"https://www.wikidata.org/wiki/Q1187693","display_name":"Control flow graph","level":2,"score":0.49374255537986755},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.484957218170166},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46789705753326416},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4599645733833313},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4466245770454407},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4280354082584381},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3146573305130005},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.27259963750839233},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2555949091911316},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/isvlsi.2004.1339528","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2004.1339528","pdf_url":null,"source":{"id":"https://openalex.org/S4306418593","display_name":"IEEE Computer Society Annual Symposium on VLSI","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:stars.library.ucf.edu:scopus2000-6010","is_oa":true,"landing_page_url":"https://stars.library.ucf.edu/scopus2000/5011","pdf_url":null,"source":{"id":"https://openalex.org/S4210172555","display_name":"Journal of International Crisis and Risk Communication Research","issn_l":"2576-0017","issn":["2576-0017","2576-0025"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Scopus Export 2000s","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.90.5604","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.90.5604","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://people.cecs.ucf.edu/ejnioui/publications/isvlsi04.pdf","raw_type":"text"}],"best_oa_location":{"id":"pmh:oai:stars.library.ucf.edu:scopus2000-6010","is_oa":true,"landing_page_url":"https://stars.library.ucf.edu/scopus2000/5011","pdf_url":null,"source":{"id":"https://openalex.org/S4210172555","display_name":"Journal of International Crisis and Risk Communication Research","issn_l":"2576-0017","issn":["2576-0017","2576-0025"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Scopus Export 2000s","raw_type":"text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1491178396","https://openalex.org/W1600303282","https://openalex.org/W1903318161","https://openalex.org/W1925866415","https://openalex.org/W2100882463","https://openalex.org/W2114732989","https://openalex.org/W2116586590","https://openalex.org/W2142386205","https://openalex.org/W2149236729","https://openalex.org/W2169238357","https://openalex.org/W4243320407","https://openalex.org/W4250661686","https://openalex.org/W6682215925"],"related_works":["https://openalex.org/W2138385884","https://openalex.org/W2166895275","https://openalex.org/W2998775986","https://openalex.org/W157564837","https://openalex.org/W2080313875","https://openalex.org/W2011536294","https://openalex.org/W4210453401","https://openalex.org/W1724049288","https://openalex.org/W2150418816","https://openalex.org/W2573637329"],"abstract_inverted_index":{"The":[0,36,59,153],"first":[1,42],"step":[2],"in":[3,28,78,134,186],"high":[4],"level":[5],"synthesis":[6],"consists":[7],"of":[8,38,55,61,82,98,104,130],"translating":[9],"a":[10,29,44,89,105,184,187],"behavioural":[11,57,102,163],"specification":[12,103],"into":[13,107],"its":[14,108,167],"corresponding":[15,109],"register":[16],"transfer":[17],"language":[18,32],"(RTL)":[19],"description.":[20],"Behavioural":[21],"specifications":[22,164],"are":[23],"composed":[24],"by":[25,41],"writing":[26],"code":[27,54],"hardware":[30],"description":[31],"such":[33],"as":[34],"VHDL.":[35],"process":[37,72],"translation":[39],"starts":[40],"deriving":[43],"control":[45],"and":[46,74,150,161,181],"data":[47],"flow":[48],"graph":[49],"(CDFG)":[50],"from":[51],"the":[52,56,62,79,99,125,131,176],"source":[53],"specification.":[58],"derivation":[60],"CDFG":[63,133,185],"has":[64,156],"been":[65,157],"mostly":[66],"done":[67],"manually,":[68],"which":[69],"makes":[70,145],"this":[71,85],"time-consuming":[73],"error-prone":[75],"at":[76],"least":[77],"earlier":[80],"stage":[81],"synthesis.":[83],"In":[84],"paper,":[86],"we":[87,92,121],"describe":[88],"tool":[90,126,147,155,177],"that":[91,175],"have":[93],"developed":[94],"for":[95,118],"automatic":[96],"conversion":[97],"given":[100],"VHDL":[101],"circuit":[106],"CDFG.":[110],"Since":[111],"there":[112],"is":[113,178],"no":[114],"widely":[115],"accepted":[116],"format":[117],"representing":[119],"CDFGs,":[120],"opted":[122],"to":[123,137,165],"make":[124],"generate":[127],"several":[128],"representations":[129],"derived":[132],"different":[135,139],"formats":[136],"accommodate":[138],"implementation":[140],"approaches.":[141],"This":[142],"design":[143],"decision":[144],"our":[146],"quite":[148],"flexible":[149],"highly":[151,179],"useful.":[152],"proposed":[154],"tested":[158],"on":[159,171],"operation":[160],"control-dominated":[162],"ensure":[166],"accuracy.":[168],"Experimental":[169],"results":[170],"benchmark":[172],"circuits":[173],"show":[174],"accurate":[180],"can":[182],"produce":[183],"few":[188],"seconds":[189],"using":[190],"minimal":[191],"computing":[192],"resources.":[193]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
