{"id":"https://openalex.org/W2122057705","doi":"https://doi.org/10.1109/isvlsi.2004.1339519","title":"Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/threshold-logic approach","display_name":"Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/threshold-logic approach","publication_year":2004,"publication_date":"2004-10-04","ids":{"openalex":"https://openalex.org/W2122057705","doi":"https://doi.org/10.1109/isvlsi.2004.1339519","mag":"2122057705"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi.2004.1339519","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2004.1339519","pdf_url":null,"source":{"id":"https://openalex.org/S4306418593","display_name":"IEEE Computer Society Annual Symposium on VLSI","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080441562","display_name":"Peter Celinski","orcid":null},"institutions":[{"id":"https://openalex.org/I5681781","display_name":"The University of Adelaide","ror":"https://ror.org/00892tw58","country_code":"AU","type":"education","lineage":["https://openalex.org/I5681781"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"P. Celinski","raw_affiliation_strings":["Centre for High Performance Integrated Technologies & Systems (CHiPTec) The Department of Electrical and Electronic Engineering, University of Adelaide, SA, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for High Performance Integrated Technologies & Systems (CHiPTec) The Department of Electrical and Electronic Engineering, University of Adelaide, SA, Australia","institution_ids":["https://openalex.org/I5681781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053660700","display_name":"Said F. Al-Sarawi","orcid":"https://orcid.org/0000-0002-3242-8197"},"institutions":[{"id":"https://openalex.org/I5681781","display_name":"The University of Adelaide","ror":"https://ror.org/00892tw58","country_code":"AU","type":"education","lineage":["https://openalex.org/I5681781"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"S. Al-Sarawi","raw_affiliation_strings":["Centre for High Performance Integrated Technologies & Systems (CHiPTec) The Department of Electrical and Electronic Engineering, University of Adelaide, SA, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for High Performance Integrated Technologies & Systems (CHiPTec) The Department of Electrical and Electronic Engineering, University of Adelaide, SA, Australia","institution_ids":["https://openalex.org/I5681781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040978000","display_name":"Derek Abbott","orcid":"https://orcid.org/0000-0002-0945-2674"},"institutions":[{"id":"https://openalex.org/I5681781","display_name":"The University of Adelaide","ror":"https://ror.org/00892tw58","country_code":"AU","type":"education","lineage":["https://openalex.org/I5681781"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"D. Abbott","raw_affiliation_strings":["Centre for High Performance Integrated Technologies & Systems (CHiPTec) The Department of Electrical and Electronic Engineering, University of Adelaide, SA, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for High Performance Integrated Technologies & Systems (CHiPTec) The Department of Electrical and Electronic Engineering, University of Adelaide, SA, Australia","institution_ids":["https://openalex.org/I5681781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057424352","display_name":"Sorin Cot\u00f6fan\u0103","orcid":"https://orcid.org/0000-0001-7132-2291"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"S. Cotofana","raw_affiliation_strings":["Computer Engineering Group Electrical Engineering Department, Delft University of Technnology, Delft, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Group Electrical Engineering Department, Delft University of Technnology, Delft, Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019437330","display_name":"S. Vassiliadis","orcid":"https://orcid.org/0000-0003-2335-1543"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"S. Vassiliadis","raw_affiliation_strings":["Computer Engineering Group Electrical Engineering Department, Delft University of Technnology, Delft, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Group Electrical Engineering Department, Delft University of Technnology, Delft, Netherlands","institution_ids":["https://openalex.org/I98358874"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.9115,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.83102944,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"2","issue":null,"first_page":"127","last_page":"132"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.7978011965751648},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7719255685806274},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6890177726745605},{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.6461412906646729},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6326767206192017},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5818398594856262},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5674383044242859},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.507044792175293},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5010402202606201},{"id":"https://openalex.org/keywords/carry","display_name":"Carry (investment)","score":0.4489981234073639},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.40452560782432556},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.38023316860198975},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.37511301040649414},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.32708513736724854},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.29714977741241455},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.17183271050453186},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15108871459960938},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1491622030735016},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.12221992015838623}],"concepts":[{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.7978011965751648},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7719255685806274},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6890177726745605},{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.6461412906646729},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6326767206192017},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5818398594856262},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5674383044242859},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.507044792175293},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5010402202606201},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.4489981234073639},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.40452560782432556},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.38023316860198975},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.37511301040649414},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.32708513736724854},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29714977741241455},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17183271050453186},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15108871459960938},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1491622030735016},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.12221992015838623},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/isvlsi.2004.1339519","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2004.1339519","pdf_url":null,"source":{"id":"https://openalex.org/S4306418593","display_name":"IEEE Computer Society Annual Symposium on VLSI","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.64.7504","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.64.7504","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://ce.et.tudelft.nl/publicationfiles/952_8_01339519.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.703.7742","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.703.7742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eleceng.adelaide.edu.au/personal/dabbott/conference/LSI_celinski2004.pdf","raw_type":"text"},{"id":"pmh:oai:digital.library.adelaide.edu.au:2440/40078","is_oa":false,"landing_page_url":"http://hdl.handle.net/2440/40078","pdf_url":null,"source":{"id":"https://openalex.org/S4306401835","display_name":"Adelaide Research & Scholarship (AR&S) (University of Adelaide)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I5681781","host_organization_name":"The University of Adelaide","host_organization_lineage":["https://openalex.org/I5681781"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://dx.doi.org/10.1109/isvlsi.2004.1339519","raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1924196901","https://openalex.org/W1959309569","https://openalex.org/W1999256336","https://openalex.org/W2029082075","https://openalex.org/W2058254562","https://openalex.org/W2088115909","https://openalex.org/W2152142824","https://openalex.org/W2160880986","https://openalex.org/W2163768479","https://openalex.org/W2789135052","https://openalex.org/W6640828704","https://openalex.org/W6664822897"],"related_works":["https://openalex.org/W2171918386","https://openalex.org/W2050591234","https://openalex.org/W2594780754","https://openalex.org/W2534190481","https://openalex.org/W2991771859","https://openalex.org/W4285230816","https://openalex.org/W2118487491","https://openalex.org/W2136656113","https://openalex.org/W2127151832","https://openalex.org/W1702497178"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,35,51,54,60,65,84],"design":[4],"exploration":[5],"of":[6,32,50,53,75],"CMOS":[7],"64-bit":[8],"adders":[9,27],"designed":[10],"using":[11,22],"threshold":[12,40],"logic":[13,41],"gates":[14],"based":[15,47],"on":[16],"systematic":[17],"transistor":[18],"level":[19],"delay":[20,44,52,74],"estimation":[21],"logical":[23],"effort":[24],"(LE).":[25],"The":[26,43],"are":[28],"hybrid":[29],"designs":[30],"consisting":[31],"domino":[33,55,86],"and":[34,56],"recently":[36],"proposed":[37],"charge":[38],"recycling":[39],"(CRTL).":[42],"evaluation":[45],"is":[46],"LE":[48],"modelling":[49],"CRTL":[57],"gates.":[58],"From":[59],"initial":[61],"estimations,":[62],"we":[63],"select":[64],"8-bit":[66],"sparse":[67],"carry":[68],"lookahead/carry-select":[69],"scheme.":[70],"Simulations":[71],"indicate":[72],"a":[73],"less":[76],"than":[77,83],"5":[78],"FO4":[79],"or":[80],"17%":[81],"faster":[82],"nearest":[85],"design.":[87]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}