{"id":"https://openalex.org/W2104010906","doi":"https://doi.org/10.1109/isvlsi.2004.1339515","title":"Behavioural scheduling to balance the bit-level computational effort","display_name":"Behavioural scheduling to balance the bit-level computational effort","publication_year":2004,"publication_date":"2004-10-04","ids":{"openalex":"https://openalex.org/W2104010906","doi":"https://doi.org/10.1109/isvlsi.2004.1339515","mag":"2104010906"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi.2004.1339515","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2004.1339515","pdf_url":null,"source":{"id":"https://openalex.org/S4306418593","display_name":"IEEE Computer Society Annual Symposium on VLSI","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009828506","display_name":"M.C. Molina","orcid":"https://orcid.org/0000-0002-9093-424X"},"institutions":[{"id":"https://openalex.org/I121748325","display_name":"Universidad Complutense de Madrid","ror":"https://ror.org/02p0gd045","country_code":"ES","type":"education","lineage":["https://openalex.org/I121748325"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"M.C. Molina","raw_affiliation_strings":["DepartmentoArquitectura de Computadores y Automatica, Universidad Complustense de Madrid, Spain","Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DepartmentoArquitectura de Computadores y Automatica, Universidad Complustense de Madrid, Spain","institution_ids":["https://openalex.org/I121748325"]},{"raw_affiliation_string":"Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain","institution_ids":["https://openalex.org/I121748325"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090728604","display_name":"R. Ruiz-Sautua","orcid":null},"institutions":[{"id":"https://openalex.org/I121748325","display_name":"Universidad Complutense de Madrid","ror":"https://ror.org/02p0gd045","country_code":"ES","type":"education","lineage":["https://openalex.org/I121748325"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"R. Ruiz-Sautua","raw_affiliation_strings":["DepartmentoArquitectura de Computadores y Automatica, Universidad Complustense de Madrid, Spain","Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DepartmentoArquitectura de Computadores y Automatica, Universidad Complustense de Madrid, Spain","institution_ids":["https://openalex.org/I121748325"]},{"raw_affiliation_string":"Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain","institution_ids":["https://openalex.org/I121748325"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020729196","display_name":"J.M. Mend\u0131\u0301as","orcid":"https://orcid.org/0000-0003-2142-338X"},"institutions":[{"id":"https://openalex.org/I121748325","display_name":"Universidad Complutense de Madrid","ror":"https://ror.org/02p0gd045","country_code":"ES","type":"education","lineage":["https://openalex.org/I121748325"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J.M. Mendias","raw_affiliation_strings":["DepartmentoArquitectura de Computadores y Automatica, Universidad Complustense de Madrid, Spain","Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DepartmentoArquitectura de Computadores y Automatica, Universidad Complustense de Madrid, Spain","institution_ids":["https://openalex.org/I121748325"]},{"raw_affiliation_string":"Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain","institution_ids":["https://openalex.org/I121748325"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011649907","display_name":"R. Hermida","orcid":"https://orcid.org/0000-0002-8022-6098"},"institutions":[{"id":"https://openalex.org/I121748325","display_name":"Universidad Complutense de Madrid","ror":"https://ror.org/02p0gd045","country_code":"ES","type":"education","lineage":["https://openalex.org/I121748325"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"R. Hermida","raw_affiliation_strings":["DepartmentoArquitectura de Computadores y Automatica, Universidad Complustense de Madrid, Spain","Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DepartmentoArquitectura de Computadores y Automatica, Universidad Complustense de Madrid, Spain","institution_ids":["https://openalex.org/I121748325"]},{"raw_affiliation_string":"Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain","institution_ids":["https://openalex.org/I121748325"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16806723,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"cad 5","issue":null,"first_page":"99","last_page":"104"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7627546787261963},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.7326695322990417},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6220800280570984},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.5717112421989441},{"id":"https://openalex.org/keywords/processor-scheduling","display_name":"Processor scheduling","score":0.5414100289344788},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5198745727539062},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.5139033794403076},{"id":"https://openalex.org/keywords/job-shop-scheduling","display_name":"Job shop scheduling","score":0.4399334490299225},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38446927070617676},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3360954523086548},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.32182562351226807},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2482304871082306},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.21996307373046875},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.2168344259262085},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10278394818305969},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09558647871017456},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08426529169082642}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7627546787261963},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.7326695322990417},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6220800280570984},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.5717112421989441},{"id":"https://openalex.org/C2984822820","wikidata":"https://www.wikidata.org/wiki/Q1123036","display_name":"Processor scheduling","level":3,"score":0.5414100289344788},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5198745727539062},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.5139033794403076},{"id":"https://openalex.org/C55416958","wikidata":"https://www.wikidata.org/wiki/Q6206757","display_name":"Job shop scheduling","level":3,"score":0.4399334490299225},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38446927070617676},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3360954523086548},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.32182562351226807},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2482304871082306},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.21996307373046875},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.2168344259262085},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10278394818305969},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09558647871017456},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08426529169082642},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/isvlsi.2004.1339515","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2004.1339515","pdf_url":null,"source":{"id":"https://openalex.org/S4306418593","display_name":"IEEE Computer Society Annual Symposium on VLSI","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.116.9445","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.116.9445","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://artecs.dacya.ucm.es/atc/descargar.php?file=molina_isvlsi04.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1587720547","https://openalex.org/W1597320861","https://openalex.org/W1830587646","https://openalex.org/W2040681925","https://openalex.org/W2093842169","https://openalex.org/W2096059450","https://openalex.org/W2098559142","https://openalex.org/W2128054489","https://openalex.org/W2129891179","https://openalex.org/W2143176263","https://openalex.org/W2158966264","https://openalex.org/W4235638977","https://openalex.org/W4237025662","https://openalex.org/W6635113191","https://openalex.org/W6674623131"],"related_works":["https://openalex.org/W1903431847","https://openalex.org/W2166021916","https://openalex.org/W1839177134","https://openalex.org/W2004001588","https://openalex.org/W2135482679","https://openalex.org/W2084005807","https://openalex.org/W1994884893","https://openalex.org/W2137686989","https://openalex.org/W2375695813","https://openalex.org/W2073831404"],"abstract_inverted_index":{"Conventional":[0],"synthesis":[1],"algorithms":[2,116],"schedule":[3],"multiple":[4],"precision":[5],"specifications":[6,38],"(formed":[7],"by":[8,13],"operations":[9,18,67,87,96],"of":[10,17,19,70,82,86,103,123],"different":[11,21],"widths)":[12],"balancing":[14],"the":[15,78,83,120],"number":[16],"every":[20],"type":[22],"and":[23,43,106],"width":[24],"executed":[25,99],"per":[26],"cycle.":[27],"However,":[28],"totally":[29],"balanced":[30],"schedules":[31],"are":[32,74],"not":[33],"always":[34],"possible,":[35],"even":[36],"for":[37],"with":[39,114],"a":[40,52,101],"unique":[41],"width,":[42],"therefore":[44],"some":[45,94],"hardware":[46,59,110,124],"waste":[47,60],"appears.":[48],"In":[49,92,112],"this":[50,58],"paper":[51],"heuristic":[53],"scheduling":[54],"algorithm":[55],"to":[56,118],"minimize":[57],"is":[61,90,139],"presented.":[62],"It":[63],"successively":[64],"transforms":[65],"specification":[66,95],"into":[68],"sets":[69],"smaller":[71],"ones":[72],"which":[73],"scheduled":[75],"independently,":[76],"until":[77],"most":[79,134],"uniform":[80],"distribution":[81],"computational":[84],"effort":[85],"among":[88],"cycles":[89,137],"achieved.":[91],"consequence":[93],"may":[97],"be":[98],"during":[100],"set":[102],"non-consecutive":[104],"cycles,":[105],"over":[107],"several":[108],"linked":[109],"resources.":[111],"combination":[113],"allocation":[115],"able":[117],"guarantee":[119],"bit-level":[121],"reuse":[122],"resources,":[125],"our":[126],"approach":[127],"substantially":[128],"reduces":[129],"datapath":[130],"area.":[131],"Additionally,":[132],"in":[133],"cases":[135],"clock":[136],"length":[138],"also":[140],"lessened.":[141]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
