{"id":"https://openalex.org/W2147941574","doi":"https://doi.org/10.1109/isvlsi.2003.1183478","title":"Decoder-based multi-context interconnect architecture","display_name":"Decoder-based multi-context interconnect architecture","publication_year":2003,"publication_date":"2003-10-01","ids":{"openalex":"https://openalex.org/W2147941574","doi":"https://doi.org/10.1109/isvlsi.2003.1183478","mag":"2147941574"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi.2003.1183478","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2003.1183478","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083656325","display_name":"Andrea Lodi","orcid":"https://orcid.org/0000-0001-9269-633X"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Lodi","raw_affiliation_strings":["ARCES, University of Bologna 2, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARCES, University of Bologna 2, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089473560","display_name":"Luca Ciccarelli","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Ciccarelli","raw_affiliation_strings":["ARCES, University of Bologna 2, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARCES, University of Bologna 2, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078015556","display_name":"Andrea Cappelli","orcid":"https://orcid.org/0000-0003-1306-4698"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Cappelli","raw_affiliation_strings":["ARCES, University of Bologna 2, Bologna, Italy","Universita di Bologna, Bologna, Emilia-Romagna, IT"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARCES, University of Bologna 2, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Universita di Bologna, Bologna, Emilia-Romagna, IT","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084295070","display_name":"F. Carnpi","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"F. Carnpi","raw_affiliation_strings":["ARCES, Bologna Univ., Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARCES, Bologna Univ., Italy","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057024890","display_name":"Mihai Filip TOMA","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Toma","raw_affiliation_strings":["ARCES, University of Bologna 2, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARCES, University of Bologna 2, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2477,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.578125,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"231","last_page":"233"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8317240476608276},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8008788228034973},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.800112247467041},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7735352516174316},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.6738495230674744},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6394058465957642},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5720288157463074},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5559301376342773},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.44803640246391296},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11536005139350891},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08760130405426025}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8317240476608276},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8008788228034973},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.800112247467041},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7735352516174316},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.6738495230674744},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6394058465957642},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5720288157463074},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5559301376342773},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.44803640246391296},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11536005139350891},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08760130405426025},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/isvlsi.2003.1183478","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2003.1183478","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.polymtl.ca:25714","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/25714/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Communication de conf\u00e9rence"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities","score":0.7599999904632568}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2068041061","https://openalex.org/W2122821503","https://openalex.org/W2127936519","https://openalex.org/W2155814884","https://openalex.org/W2168244800","https://openalex.org/W2764768456"],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2096938998"],"abstract_inverted_index":{"Multi-context":[0],"FPGAs":[1,67],"are":[2,62],"a":[3,42,71],"convenient":[4],"solution":[5,73],"for":[6,74],"run-time":[7],"reconfiguration,":[8],"but":[9],"they":[10],"suffer":[11],"from":[12],"large":[13],"area":[14,54],"occupation.":[15],"This":[16],"is":[17,47],"mainly":[18],"due":[19],"to":[20,27,59],"programmable":[21],"interconnect":[22,45],"configuration":[23],"memories":[24],"which":[25],"need":[26],"be":[28],"replicated":[29],"as":[30,33],"many":[31],"times":[32],"the":[34],"number":[35],"of":[36,53],"contexts.":[37],"To":[38],"overcome":[39],"this":[40],"limitation":[41],"new":[43],"decoder-based":[44],"architecture":[46],"proposed.":[48],"Dramatic":[49],"improvements":[50],"in":[51],"terms":[52],"and":[55],"delay":[56],"with":[57],"respect":[58],"previous":[60],"approaches":[61],"presented,":[63],"such":[64],"that":[65],"multi-context":[66],"can":[68],"finally":[69],"become":[70],"viable":[72],"next":[75],"generation":[76],"configurable":[77],"devices.":[78]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}