{"id":"https://openalex.org/W2150997368","doi":"https://doi.org/10.1109/isvlsi.2003.1183463","title":"Block-wise extraction of Rent's exponents for an extensible processor","display_name":"Block-wise extraction of Rent's exponents for an extensible processor","publication_year":2003,"publication_date":"2003-10-01","ids":{"openalex":"https://openalex.org/W2150997368","doi":"https://doi.org/10.1109/isvlsi.2003.1183463","mag":"2150997368"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi.2003.1183463","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2003.1183463","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081481126","display_name":"Tapani Ahonen","orcid":"https://orcid.org/0000-0003-0304-8790"},"institutions":[{"id":"https://openalex.org/I155660961","display_name":"University of Turku","ror":"https://ror.org/05vghhr25","country_code":"FI","type":"education","lineage":["https://openalex.org/I155660961"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"T. Ahonen","raw_affiliation_strings":["Tampere University of Technology, and University of Turku, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tampere University of Technology, and University of Turku, Finland","institution_ids":["https://openalex.org/I155660961","https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054587273","display_name":"T. Nurmi","orcid":null},"institutions":[{"id":"https://openalex.org/I155660961","display_name":"University of Turku","ror":"https://ror.org/05vghhr25","country_code":"FI","type":"education","lineage":["https://openalex.org/I155660961"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"T. Nurmi","raw_affiliation_strings":["Tampere University of Technology, and University of Turku, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tampere University of Technology, and University of Turku, Finland","institution_ids":["https://openalex.org/I155660961","https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035297149","display_name":"Jari Nurmi","orcid":"https://orcid.org/0000-0003-2169-4606"},"institutions":[{"id":"https://openalex.org/I155660961","display_name":"University of Turku","ror":"https://ror.org/05vghhr25","country_code":"FI","type":"education","lineage":["https://openalex.org/I155660961"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"J. Nurmi","raw_affiliation_strings":["Tampere University of Technology, and University of Turku, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tampere University of Technology, and University of Turku, Finland","institution_ids":["https://openalex.org/I155660961","https://openalex.org/I4210133110"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055846108","display_name":"Jouni Isoaho","orcid":"https://orcid.org/0000-0002-5789-3992"},"institutions":[{"id":"https://openalex.org/I155660961","display_name":"University of Turku","ror":"https://ror.org/05vghhr25","country_code":"FI","type":"education","lineage":["https://openalex.org/I155660961"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"J. Isoaho","raw_affiliation_strings":["Tampere University of Technology, and University of Turku, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tampere University of Technology, and University of Turku, Finland","institution_ids":["https://openalex.org/I155660961","https://openalex.org/I4210133110"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.7342,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.85507111,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"193","last_page":"199"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.760402262210846},{"id":"https://openalex.org/keywords/extensibility","display_name":"Extensibility","score":0.6816864013671875},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.6005327105522156},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5671878457069397},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.5272915363311768},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.47764861583709717},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4684949517250061},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.46002593636512756},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.44877469539642334},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.43838411569595337},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4364301562309265},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3889516294002533},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37487292289733887},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36317896842956543},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2667941451072693},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.25600698590278625},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.19322600960731506},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10806167125701904},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08602842688560486}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.760402262210846},{"id":"https://openalex.org/C32833848","wikidata":"https://www.wikidata.org/wiki/Q4115054","display_name":"Extensibility","level":2,"score":0.6816864013671875},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.6005327105522156},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5671878457069397},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.5272915363311768},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.47764861583709717},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4684949517250061},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.46002593636512756},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.44877469539642334},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.43838411569595337},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4364301562309265},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3889516294002533},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37487292289733887},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36317896842956543},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2667941451072693},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.25600698590278625},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.19322600960731506},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10806167125701904},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08602842688560486},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/isvlsi.2003.1183463","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2003.1183463","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.585.8844","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.585.8844","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://edu.cs.tut.fi/complain/TUTpublications/tapania_ISVLSI03.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W82597767","https://openalex.org/W282155574","https://openalex.org/W1556480701","https://openalex.org/W1603717301","https://openalex.org/W1970296212","https://openalex.org/W1975694818","https://openalex.org/W2014919362","https://openalex.org/W2015540924","https://openalex.org/W2037181055","https://openalex.org/W2042882340","https://openalex.org/W2125639330"],"related_works":["https://openalex.org/W2168940796","https://openalex.org/W4282568311","https://openalex.org/W4313484792","https://openalex.org/W2192917744","https://openalex.org/W2951473296","https://openalex.org/W2883928845","https://openalex.org/W4288420200","https://openalex.org/W3145095675","https://openalex.org/W2024329643","https://openalex.org/W4365793791"],"abstract_inverted_index":{"It":[0],"is":[1,56],"envisioned":[2],"that":[3],"future":[4],"system-on-chip":[5],"hardware":[6],"platform":[7],"designs":[8],"will":[9],"be":[10],"based":[11],"on":[12,86,99],"reuse":[13],"of":[14,40,51,81,89],"a":[15],"customizable":[16],"processor":[17,54,59],"core.":[18],"Consequently,":[19],"being":[20],"able":[21],"to":[22],"quickly":[23],"evaluate":[24],"the":[25,34,70,77,87,100],"key":[26],"performance":[27,45,91],"metrics":[28],"associated":[29],"with":[30,64],"specific":[31],"points":[32],"in":[33],"design":[35,43,83,102],"space":[36,84],"becomes":[37],"essential.":[38],"Development":[39],"an":[41,52],"early":[42],"phase":[44],"estimation":[46,92],"method":[47],"for":[48,67],"logic":[49],"blocks":[50,60],"extensible":[53],"core":[55],"described.":[57],"The":[58,79],"were":[61,74],"systematically":[62],"synthesized":[63],"varying":[65],"constraints":[66],"reference":[68],"and":[69],"corresponding":[71],"Rent's":[72],"exponents":[73],"extracted":[75],"from":[76],"results.":[78],"impact":[80],"synthesis-originated":[82],"discontinuities":[85],"accuracy":[88],"physical":[90],"was":[93],"evaluated":[94],"by":[95],"applying":[96],"linear":[97],"regression":[98],"resulting":[101],"points.":[103]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
