{"id":"https://openalex.org/W2119677480","doi":"https://doi.org/10.1109/isvlsi.2002.1016885","title":"A network on chip architecture and design methodology","display_name":"A network on chip architecture and design methodology","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2119677480","doi":"https://doi.org/10.1109/isvlsi.2002.1016885","mag":"2119677480"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi.2002.1016885","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2002.1016885","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047978258","display_name":"Shashi Kumar","orcid":"https://orcid.org/0000-0001-7192-1526"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"S. Kumar","raw_affiliation_strings":["Laboratory of Electronics and Computer Systems Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden","Lab. of Electron. & Comput. Syst., R. Inst. of Technol., Stockholm, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratory of Electronics and Computer Systems Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]},{"raw_affiliation_string":"Lab. of Electron. & Comput. Syst., R. Inst. of Technol., Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032163732","display_name":"Axel Jantsch","orcid":"https://orcid.org/0000-0003-2251-0004"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"A. Jantsch","raw_affiliation_strings":["Laboratory of Electronics and Computer Systems Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden","Lab. of Electron. & Comput. Syst., R. Inst. of Technol., Stockholm, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratory of Electronics and Computer Systems Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]},{"raw_affiliation_string":"Lab. of Electron. & Comput. Syst., R. Inst. of Technol., Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013862073","display_name":"Juha-Pekka Soininen","orcid":"https://orcid.org/0000-0002-7255-5318"},"institutions":[{"id":"https://openalex.org/I87653560","display_name":"VTT Technical Research Centre of Finland","ror":"https://ror.org/04b181w54","country_code":"FI","type":"nonprofit","lineage":["https://openalex.org/I4210089493","https://openalex.org/I87653560"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"J.-P. Soininen","raw_affiliation_strings":["VTT Electronics, Oulu, Finland","[VTT Electronics, Oulu, Finland]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VTT Electronics, Oulu, Finland","institution_ids":["https://openalex.org/I87653560"]},{"raw_affiliation_string":"[VTT Electronics, Oulu, Finland]","institution_ids":["https://openalex.org/I87653560"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091679053","display_name":"Martti Forsell","orcid":"https://orcid.org/0000-0003-4865-8058"},"institutions":[{"id":"https://openalex.org/I87653560","display_name":"VTT Technical Research Centre of Finland","ror":"https://ror.org/04b181w54","country_code":"FI","type":"nonprofit","lineage":["https://openalex.org/I4210089493","https://openalex.org/I87653560"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"M. Forsell","raw_affiliation_strings":["VTT Electronics, Oulu, Finland","[VTT Electronics, Oulu, Finland]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VTT Electronics, Oulu, Finland","institution_ids":["https://openalex.org/I87653560"]},{"raw_affiliation_string":"[VTT Electronics, Oulu, Finland]","institution_ids":["https://openalex.org/I87653560"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016779762","display_name":"Mikael Millberg","orcid":null},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"M. Millberg","raw_affiliation_strings":["Laboratory of Electronics and Computer Systems Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden","[Laboratory of Electronics and Computer Systems, Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratory of Electronics and Computer Systems Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]},{"raw_affiliation_string":"[Laboratory of Electronics and Computer Systems, Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden]","institution_ids":["https://openalex.org/I86987016"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008852459","display_name":"Johnny \u00d6berg","orcid":"https://orcid.org/0000-0002-8072-1742"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"J. Oberg","raw_affiliation_strings":["Laboratory of Electronics and Computer Systems Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden","[Laboratory of Electronics and Computer Systems, Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratory of Electronics and Computer Systems Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]},{"raw_affiliation_string":"[Laboratory of Electronics and Computer Systems, Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden]","institution_ids":["https://openalex.org/I86987016"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087798619","display_name":"Kari Tiensyrj\u00e4","orcid":null},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"K. Tiensyrja","raw_affiliation_strings":["Royal Institute of Technology, Stockholm, Sweden","Royal Inst., of Technology, Stockholm, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Royal Institute of Technology, Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]},{"raw_affiliation_string":"Royal Inst., of Technology, Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026355063","display_name":"Ahmed Hemani","orcid":"https://orcid.org/0000-0003-0565-9376"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"A. Hemani","raw_affiliation_strings":["Department of Microelectronics and Information Technology Royal Institute of Technology, VTT Electronics and Infotech, Stockholm, Sweden","[Department of Microelectronics and Information Technology Royal Institute of Technology, VTT Electronics and Infotech, Stockholm, Sweden]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Microelectronics and Information Technology Royal Institute of Technology, VTT Electronics and Infotech, Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]},{"raw_affiliation_string":"[Department of Microelectronics and Information Technology Royal Institute of Technology, VTT Electronics and Infotech, Stockholm, Sweden]","institution_ids":["https://openalex.org/I86987016"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":70.0704,"has_fulltext":false,"cited_by_count":1205,"citation_normalized_percentile":{"value":0.9993673,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":98,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"117","last_page":"124"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7091550827026367},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5840302109718323},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5797273516654968},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.525402843952179},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.525235652923584},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.516669511795044},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4952165186405182},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.49107956886291504},{"id":"https://openalex.org/keywords/network-architecture","display_name":"Network architecture","score":0.4292859137058258},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3907555341720581},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38525134325027466}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7091550827026367},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5840302109718323},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5797273516654968},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.525402843952179},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.525235652923584},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.516669511795044},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4952165186405182},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.49107956886291504},{"id":"https://openalex.org/C193415008","wikidata":"https://www.wikidata.org/wiki/Q639681","display_name":"Network architecture","level":2,"score":0.4292859137058258},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3907555341720581},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38525134325027466},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/isvlsi.2002.1016885","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2002.1016885","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.222.2491","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.222.2491","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.imit.kth.se/%7Eaxel/papers/2002/ISVLSI.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.473.9542","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.473.9542","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://mjpegcore.googlecode.com/files/paper20.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6100000143051147,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321855","display_name":"Tekes","ror":"https://ror.org/02ag8cq23"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W28098811","https://openalex.org/W1548168045","https://openalex.org/W1561157983","https://openalex.org/W1965748010","https://openalex.org/W2014919362","https://openalex.org/W2044570526","https://openalex.org/W2090694109","https://openalex.org/W2109259551","https://openalex.org/W2113576345","https://openalex.org/W2119122672","https://openalex.org/W2123184444","https://openalex.org/W2151415616","https://openalex.org/W2151888078","https://openalex.org/W2160664825","https://openalex.org/W3049726363","https://openalex.org/W4246955032","https://openalex.org/W4247934393","https://openalex.org/W6633748229","https://openalex.org/W6641532272","https://openalex.org/W6677210598","https://openalex.org/W6677907928","https://openalex.org/W6782143708","https://openalex.org/W6835467086"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W4863605","https://openalex.org/W4285287318","https://openalex.org/W4400409835","https://openalex.org/W2784141701","https://openalex.org/W3170183406"],"abstract_inverted_index":{"We":[0,57,156],"propose":[1],"a":[2,40,59,99,105,161,212,260],"packet":[3],"switched":[4],"platform":[5],"for":[6],"single":[7],"chip":[8],"systems":[9],"which":[10,23,116,163],"scales":[11],"well":[12],"to":[13,80,92,179,258],"an":[14,103,165],"arbitrary":[15],"number":[16,169,227,243],"of":[17,44,62,66,127,151,160,167,170,205,228,232,239,246],"processor":[18,100],"like":[19],"resources.":[20,247],"The":[21,36,130,200,222,248],"platform,":[22],"we":[24],"call":[25],"Network-on-Chip":[26],"(NOC),":[27],"includes":[28],"both":[29],"the":[30,33,51,55,63,119,125,128,135,140,143,148,152,158,177,209,218,226,233,235,242,252,255],"architecture":[31,38,132,214,224,257],"and":[32,46,68,72,83,87,122,147,172,230,237,241,244],"design":[34,74,202],"methodology.":[35],"NOC":[37,131,178,201,220],"is":[39,78,90,134,215],"m/spl":[41],"times/n":[42],"mesh":[43,65],"switches":[45,67,229],"resources":[47,69,171,182,194],"are":[48],"placed":[49],"on":[50],"slots":[52],"formed":[53],"by":[54],"switches.":[56,173],"assume":[58],"direct":[60],"layout":[61],"2-D":[64],"providing":[70],"physical-":[71],"architectural-level":[73],"integration.":[75],"Each":[76],"switch":[77],"connected":[79,91],"one":[81,93],"resource":[82,89,96],"four":[84],"neighboring":[85],"switches,":[86],"each":[88],"switch.":[94],"A":[95],"can":[97],"be":[98],"core,":[101],"memory,":[102],"FPGA,":[104],"custom":[106],"hardware":[107],"block":[108],"or":[109,190],"any":[110,168],"other":[111],"intellectual":[112],"property":[113],"(IP)":[114],"block,":[115],"fits":[117],"into":[118],"available":[120],"slot":[121],"complies":[123],"with":[124],"interface":[126],"NOC.":[129],"essentially":[133],"onchip":[136],"communication":[137],"infrastructure":[138],"comprising":[139],"physical":[141],"layer,":[142],"data":[144],"link":[145],"layer":[146,150],"network":[149],"OSI":[153],"protocol":[154],"stack.":[155],"define":[157],"concept":[159,175],"region,":[162],"occupies":[164],"area":[166],"This":[174],"allows":[176],"accommodate":[180],"large":[181,185],"such":[183,195],"as":[184,196],"memory":[186],"banks,":[187],"FPGA":[188],"areas,":[189],"special":[191],"purpose":[192],"computation":[193],"high":[197],"performance":[198],"multi-processors.":[199],"methodology":[203],"consists":[204],"two":[206],"phases.":[207],"In":[208],"first":[210],"phase":[211,250],"concrete":[213,223,256,261],"derived":[216],"from":[217],"general":[219],"template.":[221],"defines":[225],"shape":[231,238],"network,":[234],"kind":[236,245],"regions":[240],"second":[249],"maps":[251],"application":[253],"onto":[254],"form":[259],"product.":[262]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":9},{"year":2024,"cited_by_count":14},{"year":2023,"cited_by_count":23},{"year":2022,"cited_by_count":12},{"year":2021,"cited_by_count":31},{"year":2020,"cited_by_count":25},{"year":2019,"cited_by_count":29},{"year":2018,"cited_by_count":27},{"year":2017,"cited_by_count":35},{"year":2016,"cited_by_count":40},{"year":2015,"cited_by_count":42},{"year":2014,"cited_by_count":56},{"year":2013,"cited_by_count":60},{"year":2012,"cited_by_count":80}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}