{"id":"https://openalex.org/W2146669335","doi":"https://doi.org/10.1109/isvlsi.2002.1016882","title":"VLSI implementation for MAC-level DWT architecture","display_name":"VLSI implementation for MAC-level DWT architecture","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2146669335","doi":"https://doi.org/10.1109/isvlsi.2002.1016882","mag":"2146669335"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi.2002.1016882","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2002.1016882","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037745874","display_name":"Shiuh-Rong Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shiuh-Rong Huang","raw_affiliation_strings":["Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053658433","display_name":"Lan-Rong Dung","orcid":"https://orcid.org/0000-0002-7231-7029"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Lan-Rong Dung","raw_affiliation_strings":["Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.27950117,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":null,"first_page":"101","last_page":"106"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11233","display_name":"Advanced Adaptive Filtering Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2206","display_name":"Computational Mechanics"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7533848285675049},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7152950167655945},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5176647305488586},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5152649879455566},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.48799461126327515},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.48492056131362915},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.48236674070358276},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.42692556977272034},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.4203723073005676},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3930635154247284},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36665332317352295},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.34276509284973145},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.3293464481830597},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.30712032318115234},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30392324924468994},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.294376403093338},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09998899698257446}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7533848285675049},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7152950167655945},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5176647305488586},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5152649879455566},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.48799461126327515},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.48492056131362915},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.48236674070358276},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.42692556977272034},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.4203723073005676},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3930635154247284},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36665332317352295},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.34276509284973145},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.3293464481830597},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.30712032318115234},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30392324924468994},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.294376403093338},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09998899698257446},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvlsi.2002.1016882","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2002.1016882","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320323443","display_name":"National Chiao Tung University","ror":"https://ror.org/00se2k293"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1565971030","https://openalex.org/W1578812358","https://openalex.org/W1591500140","https://openalex.org/W1835805965","https://openalex.org/W2091920794","https://openalex.org/W2105609117","https://openalex.org/W2114543224","https://openalex.org/W2115443398","https://openalex.org/W2135598843","https://openalex.org/W2155962605","https://openalex.org/W6638523289"],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W2082432309","https://openalex.org/W817174743","https://openalex.org/W4254559750","https://openalex.org/W2998315020","https://openalex.org/W3016208414","https://openalex.org/W2050492524","https://openalex.org/W2352374383","https://openalex.org/W1980880153","https://openalex.org/W1978911128"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,14,44],"VLSI":[4],"design":[5],"methodology":[6],"for":[7,35,85],"the":[8,28,36,52,62,67,71,78,86,89,100],"MAC-level":[9,39,90],"DWT":[10,40,50,68,91],"processor":[11],"based":[12],"on":[13],"novel":[15],"limited-resource":[16,29],"scheduling":[17,37,58],"(LRS)":[18],"algorithm.":[19],"The":[20],"r-split":[21],"Fully-specified":[22],"Signal":[23],"Flow":[24],"Graph":[25],"(FSFG)":[26],"of":[27,38,46,80],"FIR":[30,81],"filter":[31],"has":[32,73],"been":[33,75],"developed":[34],"signal":[41],"processing.":[42],"Given":[43],"set":[45],"architecture":[47,92],"constraints":[48],"and":[49,70],"parameters,":[51],"LRS":[53],"algorithm":[54],"can":[55],"generate":[56],"four":[57],"matrices":[59],"that":[60],"drive":[61],"data":[63],"path":[64],"to":[65],"perform":[66],"computation,":[69],"performance":[72],"also":[74],"investigated.":[76],"Because":[77],"registers":[79],"filtering":[82],"are":[83],"reused":[84],"inter-octave":[87,97],"storage,":[88],"may":[93],"require":[94],"less":[95],"extra":[96],"memory":[98],"than":[99],"traditional":[101],"architecture.":[102]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}