{"id":"https://openalex.org/W2167971065","doi":"https://doi.org/10.1109/isvlsi.2002.1016881","title":"High-performance field programmable VLSI processor based on a direct allocation of a control/data flow graph","display_name":"High-performance field programmable VLSI processor based on a direct allocation of a control/data flow graph","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2167971065","doi":"https://doi.org/10.1109/isvlsi.2002.1016881","mag":"2167971065"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi.2002.1016881","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2002.1016881","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://tohoku.repo.nii.ac.jp/record/66905/files/10.1109-ISVLSI.2002.1016881.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084918111","display_name":"N. Ohsawa","orcid":null},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"N. Ohsawa","raw_affiliation_strings":["Graduate School of Information Sciences, University of Tohoku, Sendai, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, University of Tohoku, Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070647966","display_name":"Masanori Hariyama","orcid":"https://orcid.org/0000-0002-1464-8807"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Hariyama","raw_affiliation_strings":["Graduate School of Information Sciences, University of Tohoku, Sendai, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, University of Tohoku, Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037191455","display_name":"Michitaka Kameyama","orcid":"https://orcid.org/0000-0002-4245-9907"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Kameyama","raw_affiliation_strings":["Graduate School of Information Sciences, University of Tohoku, Sendai, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, University of Tohoku, Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I201537933"],"apc_list":null,"apc_paid":null,"fwci":1.0482,"has_fulltext":true,"cited_by_count":14,"citation_normalized_percentile":{"value":0.81668826,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"7","issue":null,"first_page":"95","last_page":"100"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7576173543930054},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7224279642105103},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.665656566619873},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6572020649909973},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.5416484475135803},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4787423014640808},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4672930836677551},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44550174474716187},{"id":"https://openalex.org/keywords/control-flow-graph","display_name":"Control flow graph","score":0.42021384835243225},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39239323139190674},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3470528721809387},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11966407299041748},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11174759268760681},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.08198583126068115}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7576173543930054},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7224279642105103},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.665656566619873},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6572020649909973},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.5416484475135803},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4787423014640808},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4672930836677551},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44550174474716187},{"id":"https://openalex.org/C27458966","wikidata":"https://www.wikidata.org/wiki/Q1187693","display_name":"Control flow graph","level":2,"score":0.42021384835243225},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39239323139190674},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3470528721809387},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11966407299041748},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11174759268760681},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.08198583126068115},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/isvlsi.2002.1016881","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2002.1016881","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","raw_type":"proceedings-article"},{"id":"pmh:oai:irdb.nii.ac.jp:00918:0000486962","is_oa":true,"landing_page_url":"https://tohoku.repo.nii.ac.jp/records/66905","pdf_url":"https://tohoku.repo.nii.ac.jp/record/66905/files/10.1109-ISVLSI.2002.1016881.pdf","source":{"id":"https://openalex.org/S7407056385","display_name":"Institutional Repositories DataBase (IRDB)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I184597095","host_organization_name":"National Institute of Informatics","host_organization_lineage":["https://openalex.org/I184597095"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings. IEEE Computer Society Annual Symposium on VLSI, 2002.","raw_type":"journal article"}],"best_oa_location":{"id":"pmh:oai:irdb.nii.ac.jp:00918:0000486962","is_oa":true,"landing_page_url":"https://tohoku.repo.nii.ac.jp/records/66905","pdf_url":"https://tohoku.repo.nii.ac.jp/record/66905/files/10.1109-ISVLSI.2002.1016881.pdf","source":{"id":"https://openalex.org/S7407056385","display_name":"Institutional Repositories DataBase (IRDB)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I184597095","host_organization_name":"National Institute of Informatics","host_organization_lineage":["https://openalex.org/I184597095"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings. IEEE Computer Society Annual Symposium on VLSI, 2002.","raw_type":"journal article"},"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2167971065.pdf","grobid_xml":"https://content.openalex.org/works/W2167971065.grobid-xml"},"referenced_works_count":3,"referenced_works":["https://openalex.org/W2137265220","https://openalex.org/W2584091468","https://openalex.org/W2584901933"],"related_works":["https://openalex.org/W2081032080","https://openalex.org/W2134733504","https://openalex.org/W2144460576","https://openalex.org/W2151163382","https://openalex.org/W4256382613","https://openalex.org/W1549956274","https://openalex.org/W1516632679","https://openalex.org/W2144344516","https://openalex.org/W59945861","https://openalex.org/W2052160877"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,12,34,49,57,63,81],"high-performance":[4],"field":[5],"programmable":[6,25],"VLSI":[7],"processor":[8],"(FPVLSI),":[9],"in":[10,37,80],"which":[11],"bit-serial":[13],"processing":[14],"element":[15],"(PE)":[16],"array":[17],"is":[18,53,60,70,78,92],"introduced":[19],"to":[20,94],"reduce":[21],"the":[22,29,38,67,90,102,107],"complexity":[23,69],"of":[24,33,48,89,101],"interconnection":[26,39],"networks.":[27],"Therefore,":[28],"area":[30],"and":[31],"delay":[32],"switch":[35],"block":[36],"network":[40],"can":[41],"be":[42,95],"greatly":[43,71],"reduced.":[44,72],"Moreover,":[45],"direct":[46],"allocation":[47],"control/data":[50],"flow":[51],"graph":[52],"employed":[54],"where":[55],"only":[56],"single":[58],"node":[59],"mapped":[61],"into":[62],"PE":[64],"so":[65],"that":[66,100],"wiring":[68],"The":[73,87],"FPVLSI":[74,91],"with":[75],"4400":[76],"PEs":[77],"designed":[79],"0.35":[82],"/spl":[83],"mu/m":[84],"CMOS":[85],"process.":[86],"performance":[88],"evaluated":[93],"28":[96],"times":[97],"higher":[98],"than":[99],"typical":[103],"FPGA":[104],"when":[105],"executing":[106],"16-point":[108],"FFT.":[109]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}