{"id":"https://openalex.org/W2763821039","doi":"https://doi.org/10.1109/isvdat.2016.8064873","title":"Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC","display_name":"Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2763821039","doi":"https://doi.org/10.1109/isvdat.2016.8064873","mag":"2763821039"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2016.8064873","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2016.8064873","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002657145","display_name":"Moumita Chakraborty","orcid":"https://orcid.org/0000-0001-7509-1777"},"institutions":[{"id":"https://openalex.org/I1323252656","display_name":"Information Technology University","ror":"https://ror.org/00ngv8j44","country_code":"PK","type":"education","lineage":["https://openalex.org/I1323252656"]},{"id":"https://openalex.org/I106542073","display_name":"University of Calcutta","ror":"https://ror.org/01e7v7w47","country_code":"IN","type":"education","lineage":["https://openalex.org/I106542073"]}],"countries":["IN","PK"],"is_corresponding":true,"raw_author_name":"Moumita Chakraborty","raw_affiliation_strings":["School of Information Technology, University of Calcutta"],"affiliations":[{"raw_affiliation_string":"School of Information Technology, University of Calcutta","institution_ids":["https://openalex.org/I106542073","https://openalex.org/I1323252656"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043543748","display_name":"Amlan Chakrabarti","orcid":"https://orcid.org/0000-0003-4380-3172"},"institutions":[{"id":"https://openalex.org/I1323252656","display_name":"Information Technology University","ror":"https://ror.org/00ngv8j44","country_code":"PK","type":"education","lineage":["https://openalex.org/I1323252656"]},{"id":"https://openalex.org/I106542073","display_name":"University of Calcutta","ror":"https://ror.org/01e7v7w47","country_code":"IN","type":"education","lineage":["https://openalex.org/I106542073"]}],"countries":["IN","PK"],"is_corresponding":false,"raw_author_name":"Amlan Chakrabarti","raw_affiliation_strings":["School of Information Technology, University of Calcutta"],"affiliations":[{"raw_affiliation_string":"School of Information Technology, University of Calcutta","institution_ids":["https://openalex.org/I106542073","https://openalex.org/I1323252656"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102943423","display_name":"Partha Mitra","orcid":"https://orcid.org/0000-0002-1331-3538"},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Partha Mitra","raw_affiliation_strings":["Texas Instruments, Bangalore"],"affiliations":[{"raw_affiliation_string":"Texas Instruments, Bangalore","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101919576","display_name":"Debasri Saha","orcid":"https://orcid.org/0000-0002-7935-0980"},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Debasri Saha","raw_affiliation_strings":["Texas Instruments, Bangalore"],"affiliations":[{"raw_affiliation_string":"Texas Instruments, Bangalore","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002833632","display_name":"Krishnendu Guha","orcid":"https://orcid.org/0000-0003-1139-9582"},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Krishnendu Guha","raw_affiliation_strings":["Texas Instruments, Bangalore"],"affiliations":[{"raw_affiliation_string":"Texas Instruments, Bangalore","institution_ids":["https://openalex.org/I74760111"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5002657145"],"corresponding_institution_ids":["https://openalex.org/I106542073","https://openalex.org/I1323252656"],"apc_list":null,"apc_paid":null,"fwci":0.1838,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.62318267,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/decoupling-capacitor","display_name":"Decoupling capacitor","score":0.6877915859222412},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6274633407592773},{"id":"https://openalex.org/keywords/decoupling","display_name":"Decoupling (probability)","score":0.5929844975471497},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.576347291469574},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.5124137997627258},{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.512040913105011},{"id":"https://openalex.org/keywords/power-integrity","display_name":"Power integrity","score":0.4919533431529999},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.4840337634086609},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4671606123447418},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.46646320819854736},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4512389004230499},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4474680721759796},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.42157506942749023},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.3731909394264221},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3559497892856598},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.3461246192455292},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3382769227027893},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2980967164039612},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26237350702285767},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.22719576954841614},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09874939918518066}],"concepts":[{"id":"https://openalex.org/C35196352","wikidata":"https://www.wikidata.org/wiki/Q1532649","display_name":"Decoupling capacitor","level":4,"score":0.6877915859222412},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6274633407592773},{"id":"https://openalex.org/C205606062","wikidata":"https://www.wikidata.org/wiki/Q5249645","display_name":"Decoupling (probability)","level":2,"score":0.5929844975471497},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.576347291469574},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.5124137997627258},{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.512040913105011},{"id":"https://openalex.org/C2777561913","wikidata":"https://www.wikidata.org/wiki/Q19599527","display_name":"Power integrity","level":4,"score":0.4919533431529999},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.4840337634086609},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4671606123447418},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.46646320819854736},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4512389004230499},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4474680721759796},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.42157506942749023},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.3731909394264221},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3559497892856598},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.3461246192455292},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3382769227027893},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2980967164039612},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26237350702285767},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.22719576954841614},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09874939918518066},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C147789679","wikidata":"https://www.wikidata.org/wiki/Q11372","display_name":"Physical chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2016.8064873","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2016.8064873","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5899999737739563}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W27287307","https://openalex.org/W329998640","https://openalex.org/W942387266","https://openalex.org/W1521840072","https://openalex.org/W1546169179","https://openalex.org/W1616047807","https://openalex.org/W1959849065","https://openalex.org/W2029506076","https://openalex.org/W2031767704","https://openalex.org/W2062567173","https://openalex.org/W2099522624","https://openalex.org/W2102315438","https://openalex.org/W2111842505","https://openalex.org/W2112148124","https://openalex.org/W2124089733","https://openalex.org/W2124352222","https://openalex.org/W2134381910","https://openalex.org/W2149577452","https://openalex.org/W2150547314","https://openalex.org/W2163263638","https://openalex.org/W2167232953","https://openalex.org/W2408316994","https://openalex.org/W2502356983","https://openalex.org/W2580026558","https://openalex.org/W4235276082","https://openalex.org/W4242987207","https://openalex.org/W4253058520","https://openalex.org/W4253369885","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2533759086","https://openalex.org/W2898647956","https://openalex.org/W2811251486","https://openalex.org/W4239401071","https://openalex.org/W2246813539","https://openalex.org/W2067224723","https://openalex.org/W2094215088","https://openalex.org/W4255973033","https://openalex.org/W1989947234","https://openalex.org/W2010236192"],"abstract_inverted_index":{"This":[0,236],"paper":[1],"addresses":[2],"estimation":[3,108,120],"of":[4,19,59,73,100,109,124,195,200],"decoupling":[5,60],"capacitance":[6],"(decap)":[7],"at":[8,21,75,187,197,227,248],"sub-module":[9],"stage":[10,190,230],"based":[11],"on":[12,64],"their":[13],"power":[14,29,204],"dissipation":[15],"and":[16,30,39,71,92,121,133,157,175,179,191,205,214,224],"proper":[17],"allocation":[18,72,123,183],"decap":[20,182],"the":[22,45,57,79,96,113,170,181,188,198,228,233,249],"pre-layout":[23,80,189,229],"level.":[24],"Decap":[25],"being":[26],"in":[27,44,51,78,88,104,155,164,172,203,240],"between":[28],"ground":[31],"distribution":[32],"networks":[33],"acts":[34],"as":[35,143,150,161],"local":[36],"charge":[37],"storage":[38],"effectively":[40],"reduces":[41],"rapid":[42],"transients":[43],"supply":[46],"drop.":[47],"Therefore,":[48],"present":[49],"trends":[50],"VLSI":[52],"design":[53],"are":[54,158],"inclined":[55],"towards":[56],"placement":[58],"capacitors":[61],"for":[62,95,112,146,184],"system":[63],"chip":[65],"(SoC)":[66],"design.":[67],"But,":[68],"early":[69,237],"prediction":[70,238],"decaps":[74,125],"appropriate":[76,122],"locations":[77],"circuit":[81],"can":[82,218],"only":[83],"provide":[84],"a":[85],"better":[86],"scope":[87],"optimizing":[89],"power,":[90,131,173],"noise":[91,134,174,196,213,217],"delay":[93,132,176],"effects":[94],"circuit.":[97],"The":[98],"novelty":[99],"our":[101,147,209],"work":[102],"lies":[103],"exhaustive":[105],"module":[106],"wise":[107],"di/dt":[110],"drop":[111],"complete":[114],"circuit,":[115],"followed":[116],"by":[117,222],"an":[118,127],"algorithmic":[119],"with":[126,178,232],"effort":[128],"to":[129,136],"keep":[130],"performance":[135],"its":[137],"best.":[138],"We":[139,168],"choose":[140],"Double":[141],"DES":[142],"example":[144],"crypto-core":[145],"test":[148],"circuits":[149,186],"this":[151],"is":[152],"quite":[153],"complex":[154],"nature":[156],"also":[159],"used":[160],"custom":[162],"cores":[163],"many":[165],"SoC":[166],"applications.":[167],"investigate":[169],"change":[171],"parameters":[177],"without":[180],"multi-core":[185],"find":[192],"satisfactory":[193],"suppression":[194],"cost":[199],"negligible":[201],"increase":[202],"delay.":[206],"By":[207],"using":[208],"approach,":[210],"average":[211],"peak":[212,216],"maximum":[215],"be":[219],"suppressed":[220],"approximately":[221],"22.7%":[223],"32.23%":[225],"respectively":[226],"comparing":[231],"previous":[234],"works.":[235],"helps":[239],"more":[241],"accurate":[242],"Computer":[243],"Aided":[244],"Design":[245],"(CAD)":[246],"implementation":[247],"layout":[250],"stage.":[251]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
