{"id":"https://openalex.org/W2761217249","doi":"https://doi.org/10.1109/isvdat.2016.8064870","title":"Towards a dynamic associativity enabled write prediction based hybrid cache","display_name":"Towards a dynamic associativity enabled write prediction based hybrid cache","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2761217249","doi":"https://doi.org/10.1109/isvdat.2016.8064870","mag":"2761217249"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2016.8064870","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2016.8064870","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034837887","display_name":"Sukarn Agarwal","orcid":"https://orcid.org/0000-0003-1292-3235"},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Sukarn Agarwal","raw_affiliation_strings":["Department of Computer Science and Engineering, IIT, Guwahati, Assam, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, IIT, Guwahati, Assam, India","institution_ids":["https://openalex.org/I1317621060"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070605948","display_name":"Hemangee K. Kapoor","orcid":"https://orcid.org/0000-0002-9376-7686"},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Hemangee K. Kapoor","raw_affiliation_strings":["Department of Computer Science and Engineering, IIT, Guwahati, Assam, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, IIT, Guwahati, Assam, India","institution_ids":["https://openalex.org/I1317621060"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5034837887"],"corresponding_institution_ids":["https://openalex.org/I1317621060"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.22677302,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7960262298583984},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7837897539138794},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7422272562980652},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5282325744628906},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5195865631103516},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.4704275131225586},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4693022072315216},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.4636797308921814},{"id":"https://openalex.org/keywords/phase-change-memory","display_name":"Phase-change memory","score":0.44858312606811523},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.44756028056144714},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.41844624280929565},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.4180680215358734},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.4140700697898865},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3600988984107971},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.3301442265510559},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.2891605496406555},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2800922691822052},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2313465178012848},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.22655445337295532},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13552019000053406},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07786646485328674},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07052958011627197},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07007372379302979}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7960262298583984},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7837897539138794},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7422272562980652},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5282325744628906},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5195865631103516},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.4704275131225586},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4693022072315216},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.4636797308921814},{"id":"https://openalex.org/C64142963","wikidata":"https://www.wikidata.org/wiki/Q1153902","display_name":"Phase-change memory","level":3,"score":0.44858312606811523},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.44756028056144714},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.41844624280929565},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.4180680215358734},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.4140700697898865},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3600988984107971},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.3301442265510559},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2891605496406555},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2800922691822052},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2313465178012848},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.22655445337295532},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13552019000053406},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07786646485328674},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07052958011627197},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07007372379302979},{"id":"https://openalex.org/C133256868","wikidata":"https://www.wikidata.org/wiki/Q7180940","display_name":"Phase change","level":2,"score":0.0},{"id":"https://openalex.org/C61696701","wikidata":"https://www.wikidata.org/wiki/Q770766","display_name":"Engineering physics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2016.8064870","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2016.8064870","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1941299990","https://openalex.org/W1968295951","https://openalex.org/W1979955706","https://openalex.org/W2000005457","https://openalex.org/W2010202670","https://openalex.org/W2010216838","https://openalex.org/W2064977311","https://openalex.org/W2083608936","https://openalex.org/W2131926352","https://openalex.org/W2147657366","https://openalex.org/W2156159026","https://openalex.org/W2169660454","https://openalex.org/W2169875292","https://openalex.org/W2464177207","https://openalex.org/W2981757023","https://openalex.org/W4230661076","https://openalex.org/W4231378725","https://openalex.org/W4232937019","https://openalex.org/W6682917345","https://openalex.org/W6719768283","https://openalex.org/W6728964506"],"related_works":["https://openalex.org/W2133489088","https://openalex.org/W2114386333","https://openalex.org/W2126408955","https://openalex.org/W2535115842","https://openalex.org/W2115222420","https://openalex.org/W2363769136","https://openalex.org/W2396934146","https://openalex.org/W2148571123","https://openalex.org/W2391047183","https://openalex.org/W2734782074"],"abstract_inverted_index":{"Non-Volatile":[0],"Memory":[1,11,17,23],"(NVM)":[2],"technologies":[3],"such":[4],"as":[5,27,34,64,78],"Spin":[6],"Transfer":[7],"Torque":[8],"Random":[9,15,21],"Access":[10,16,22],"(STT-RAM),":[12],"Phase":[13],"Change":[14],"(PCRAM)":[18],"and":[19,51,139],"Resistive":[20],"(RERAM)":[24],"have":[25],"emerged":[26],"a":[28,65,79,90,108],"potential":[29],"replacement":[30],"for":[31,67,94],"traditional":[32],"SRAM":[33,110,138],"the":[35,115,127,136,152],"last":[36],"level":[37],"cache.":[38],"These":[39],"are":[40],"attractive":[41],"due":[42],"to":[43],"their":[44,62],"low":[45],"static":[46],"power":[47],"consumption,":[48],"higher":[49],"density":[50],"good":[52],"scalability.":[53],"However,":[54],"expensive":[55,72],"write":[56,73],"operations":[57],"in":[58],"these":[59,71],"NVMs":[60],"reduces":[61],"chances":[63],"substitute":[66],"SRAM.":[68],"To":[69],"handle":[70],"operations,":[74],"cache":[75,81,96,106,118],"is":[76,98,121,133],"designed":[77],"hybrid":[80,95,105],"consisting":[82],"of":[83,117,151,157],"different":[84],"memory":[85],"technologies.":[86],"This":[87,120],"paper":[88],"proposes":[89],"block":[91],"prediction":[92,102],"technique":[93],"that":[97],"based":[99],"on":[100],"existing":[101],"mechanism.":[103],"The":[104,130],"has":[107],"smaller":[109],"partition":[111],"which":[112],"may":[113],"limit":[114],"amount":[116],"capacity.":[119],"overcome":[122],"by":[123],"increasing":[124],"or":[125],"decreasing":[126],"associativity":[128],"dynamically.":[129],"proposed":[131],"policy":[132],"compared":[134],"with":[135,154],"baseline":[137],"STT-RAM":[140],"caches.":[141],"Experimental":[142],"results":[143],"using":[144],"full":[145],"system":[146],"simulation":[147],"shows":[148],"significant":[149],"reduction":[150],"energy":[153],"slight":[155],"improvement":[156],"performance.":[158]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}