{"id":"https://openalex.org/W2764176058","doi":"https://doi.org/10.1109/isvdat.2016.8064859","title":"New stable loadless 6T dual-port SRAM cell design","display_name":"New stable loadless 6T dual-port SRAM cell design","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2764176058","doi":"https://doi.org/10.1109/isvdat.2016.8064859","mag":"2764176058"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2016.8064859","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2016.8064859","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005995780","display_name":"Antara Ganguly","orcid":null},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]},{"id":"https://openalex.org/I119939252","display_name":"Indraprastha Institute of Information Technology Delhi","ror":"https://ror.org/03vfp4g33","country_code":"IN","type":"education","lineage":["https://openalex.org/I119939252"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Antara Ganguly","raw_affiliation_strings":["IIIT Delhi, New Delhi, India"],"affiliations":[{"raw_affiliation_string":"IIIT Delhi, New Delhi, India","institution_ids":["https://openalex.org/I119939252","https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091820561","display_name":"Sangeeta Goyal","orcid":null},"institutions":[{"id":"https://openalex.org/I119939252","display_name":"Indraprastha Institute of Information Technology Delhi","ror":"https://ror.org/03vfp4g33","country_code":"IN","type":"education","lineage":["https://openalex.org/I119939252"]},{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sangeeta Goyal","raw_affiliation_strings":["IIIT Delhi, New Delhi, India"],"affiliations":[{"raw_affiliation_string":"IIIT Delhi, New Delhi, India","institution_ids":["https://openalex.org/I119939252","https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113862887","display_name":"S.P. Bhatia","orcid":null},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]},{"id":"https://openalex.org/I119939252","display_name":"Indraprastha Institute of Information Technology Delhi","ror":"https://ror.org/03vfp4g33","country_code":"IN","type":"education","lineage":["https://openalex.org/I119939252"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sneha Bhatia","raw_affiliation_strings":["IIIT Delhi, New Delhi, India"],"affiliations":[{"raw_affiliation_string":"IIIT Delhi, New Delhi, India","institution_ids":["https://openalex.org/I119939252","https://openalex.org/I68891433"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063583051","display_name":"Anuj Grover","orcid":"https://orcid.org/0000-0002-6057-4984"},"institutions":[{"id":"https://openalex.org/I4210094169","display_name":"STMicroelectronics (India)","ror":"https://ror.org/00ft7bw25","country_code":"IN","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210094169"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anuj Grover","raw_affiliation_strings":["ST Microelectronics Greater, Noida, India"],"affiliations":[{"raw_affiliation_string":"ST Microelectronics Greater, Noida, India","institution_ids":["https://openalex.org/I4210094169"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5005995780"],"corresponding_institution_ids":["https://openalex.org/I119939252","https://openalex.org/I68891433"],"apc_list":null,"apc_paid":null,"fwci":0.1838,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.6232074,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"3","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.672808825969696},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.639559268951416},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6048200130462646},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41578882932662964},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2474331557750702},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16291233897209167}],"concepts":[{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.672808825969696},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.639559268951416},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6048200130462646},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41578882932662964},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2474331557750702},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16291233897209167}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2016.8064859","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2016.8064859","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7599999904632568,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1485745721","https://openalex.org/W1518236483","https://openalex.org/W1599944493","https://openalex.org/W1986445598","https://openalex.org/W1987559308","https://openalex.org/W1991029946","https://openalex.org/W1992346871","https://openalex.org/W2003358164","https://openalex.org/W2023362103","https://openalex.org/W2035720033","https://openalex.org/W2074611837","https://openalex.org/W2102916325","https://openalex.org/W2158436329","https://openalex.org/W2158933924","https://openalex.org/W2162335740","https://openalex.org/W2290360647","https://openalex.org/W2481702255","https://openalex.org/W2545500460","https://openalex.org/W4214569831"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W4392590355","https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W1976168335","https://openalex.org/W2109451123","https://openalex.org/W4378977321"],"abstract_inverted_index":{"Simultaneous":[0],"read":[1,49],"and":[2,64],"write":[3],"operations":[4],"without":[5],"any":[6,13],"disturbance":[7],"is":[8,85,102],"a":[9,26,72],"fundamental":[10],"expectancy":[11],"from":[12,91],"dual":[14],"port":[15,35,82,99,114],"static":[16],"random":[17],"access":[18],"memory":[19,67],"(DPSRAM)":[20],"cell":[21,31],"design.":[22],"The":[23,51,110],"paper":[24],"proposes":[25],"stable":[27],"loadless":[28],"6T":[29],"DPSRAM":[30,45],"design":[32,52,112],"with":[33,47,94],"reduced":[34],"setup":[36,83,100,115],"time":[37,56,84,101,116],"as":[38,120],"compared":[39,121],"to":[40,59,122],"that":[41],"of":[42,117,125],"standard":[43],"8T":[44,126],"along":[46],"better":[48],"stability.":[50],"has":[53,113],"lower":[54],"cycle":[55],"allowing":[57],"SRAM":[58],"operate":[60],"at":[61],"higher":[62],"frequencies":[63],"hence,":[65],"more":[66],"can":[68],"be":[69],"accessed":[70],"in":[71],"given":[73],"time.":[74],"To":[75],"preserve":[76],"the":[77],"data":[78],"integrity,":[79],"an":[80],"optimum":[81],"calculated":[86],"using":[87],"best":[88],"fit":[89],"curve":[90],"regression":[92],"plots":[93],"95%":[95],"confidence":[96],"bounds.":[97],"As":[98],"increased,":[103],"voltage":[104],"value":[105],"for":[106],"spurious":[107],"logic":[108],"reduces.":[109],"proposed":[111],"1.6":[118],"picoseconds":[119,124],"7.2":[123],"DPSRAM.":[127]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
