{"id":"https://openalex.org/W2760897110","doi":"https://doi.org/10.1109/isvdat.2016.8064843","title":"High performance bit-sliced pipelined comparator tree for FPGAs","display_name":"High performance bit-sliced pipelined comparator tree for FPGAs","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2760897110","doi":"https://doi.org/10.1109/isvdat.2016.8064843","mag":"2760897110"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2016.8064843","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2016.8064843","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051876733","display_name":"Ayan Palchaudhuri","orcid":"https://orcid.org/0000-0002-4338-6404"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Ayan Palchaudhuri","raw_affiliation_strings":["Department of Electronics & Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics & Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034075191","display_name":"Anindya Sundar Dhar","orcid":"https://orcid.org/0000-0001-5288-4715"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anindya Sundar Dhar","raw_affiliation_strings":["Department of Electronics & Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics & Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, India","institution_ids":["https://openalex.org/I145894827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5051876733"],"corresponding_institution_ids":["https://openalex.org/I145894827"],"apc_list":null,"apc_paid":null,"fwci":0.3749,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.68784419,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8196781873703003},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7905805110931396},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.7894707322120667},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7658896446228027},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6278765797615051},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.48769697546958923},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.4411528706550598},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.4337031841278076},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43243810534477234},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39200836420059204},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37356847524642944},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11805135011672974}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8196781873703003},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7905805110931396},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.7894707322120667},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7658896446228027},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6278765797615051},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.48769697546958923},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.4411528706550598},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.4337031841278076},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43243810534477234},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39200836420059204},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37356847524642944},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11805135011672974},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2016.8064843","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2016.8064843","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1501488688","https://openalex.org/W1543281322","https://openalex.org/W1550016006","https://openalex.org/W1618445774","https://openalex.org/W1944183873","https://openalex.org/W1973127083","https://openalex.org/W1979459774","https://openalex.org/W2024384999","https://openalex.org/W2031476303","https://openalex.org/W2058276166","https://openalex.org/W2114593256","https://openalex.org/W2135481592","https://openalex.org/W2139874893","https://openalex.org/W2161395307","https://openalex.org/W2293714800","https://openalex.org/W2463604510","https://openalex.org/W2477990578"],"related_works":["https://openalex.org/W2034349229","https://openalex.org/W2117300767","https://openalex.org/W2024574431","https://openalex.org/W2374017528","https://openalex.org/W4285503609","https://openalex.org/W2126248441","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2125609625"],"abstract_inverted_index":{"In":[0],"this":[1,65],"paper,":[2],"we":[3],"have":[4],"implemented":[5],"high":[6],"performance":[7],"FPGA":[8,80,174],"based":[9,52,113],"pipelined":[10],"tree":[11,112],"architectures":[12,41,81,198],"for":[13,123],"a":[14,36,91,98,111,161,205],"combined":[15,45],"unsigned":[16],"and":[17,21,49,77,131,133,137,166,202],"two's":[18],"complement":[19],"comparator,":[20],"an":[22,211],"equality":[23],"comparator":[24,40],"which":[25,54],"checks":[26],"whether":[27],"the":[28,44,58,69,75,102,108,117,125,129,149,156,167,170,173,184],"sum":[29],"of":[30,64,107,119,128,148,155,169,186,193],"two":[31],"numbers":[32],"is":[33,55],"equal":[34],"to":[35,152,210],"third":[37],"number.":[38],"The":[39,62,140],"deviate":[42],"from":[43,68,82,90],"Look-Up":[46],"Table":[47],"(LUT)":[48],"carry":[50],"chain":[51],"implementation":[53],"inferred":[56],"by":[57,74],"Xilinx":[59],"Synthesis":[60],"Tool.":[61],"feasibility":[63],"work":[66],"comes":[67],"increased":[70],"device":[71],"density":[72],"offered":[73],"6":[76],"7":[78],"series":[79],"Xilinx,":[83],"where":[84,195],"every":[85],"dual":[86,157],"output":[87,158],"function":[88],"derived":[89],"single":[92,162],"LUT":[93,163],"can":[94],"be":[95],"registered":[96],"using":[97,176,215],"flip-flop":[99],"present":[100],"within":[101],"same":[103],"slice":[104],"as":[105],"that":[106],"LUT.":[109],"Pipelining":[110],"architecture":[114,141],"completely":[115],"eliminates":[116],"requirement":[118],"any":[120],"synchronization":[121],"registers":[122],"balancing":[124],"arrival":[126],"time":[127],"inputs":[130],"outputs,":[132],"their":[134],"associated":[135],"placement":[136,168,178],"routing":[138],"challenges.":[139],"has":[142],"been":[143],"realized":[144,214],"through":[145],"primitive":[146],"instantiation":[147],"logic":[150],"elements":[151],"ensure":[153],"packing":[154],"functions":[159],"into":[160],"wherever":[164],"possible,":[165],"LUTs":[171],"on":[172],"fabric":[175],"appropriate":[177],"constraints.":[179],"Implementation":[180],"results":[181],"clearly":[182],"reveal":[183],"superiority":[185],"our":[187,196],"design":[188],"paradigm":[189],"over":[190],"behavioral":[191,216],"style":[192],"modeling,":[194],"proposed":[197],"consume":[199],"less":[200],"area,":[201],"operates":[203],"at":[204],"higher":[206],"speed":[207],"in":[208],"comparison":[209],"identical":[212],"circuit":[213],"descriptions.":[217]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
