{"id":"https://openalex.org/W1598259261","doi":"https://doi.org/10.1109/isvdat.2015.7208152","title":"A methodology to reuse random IP stimuli in an SoC functional verification environment","display_name":"A methodology to reuse random IP stimuli in an SoC functional verification environment","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W1598259261","doi":"https://doi.org/10.1109/isvdat.2015.7208152","mag":"1598259261"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2015.7208152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038027691","display_name":"V S Rashmi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"V S Rashmi","raw_affiliation_strings":["Texas Instruments (India) Pvt. Ltd., Bengaluru, India","Texas Instruments (India) Pvt., Ltd., Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Texas Instruments (India) Pvt. Ltd., Bengaluru, India","institution_ids":["https://openalex.org/I4210109535"]},{"raw_affiliation_string":"Texas Instruments (India) Pvt., Ltd., Bengaluru, India","institution_ids":["https://openalex.org/I4210109535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050338730","display_name":"Giridhar Somayaji","orcid":null},"institutions":[{"id":"https://openalex.org/I79172759","display_name":"Lantiq (Germany)","ror":"https://ror.org/01bvfdq42","country_code":"DE","type":"company","lineage":["https://openalex.org/I79172759"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Giridhar Somayaji","raw_affiliation_strings":["Lantia Semiconductors Asia, Singapore","Lantiq Semiconductors Asia, Singapore"],"affiliations":[{"raw_affiliation_string":"Lantia Semiconductors Asia, Singapore","institution_ids":[]},{"raw_affiliation_string":"Lantiq Semiconductors Asia, Singapore","institution_ids":["https://openalex.org/I79172759"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076402828","display_name":"Sirisha Bhamidipathi","orcid":null},"institutions":[{"id":"https://openalex.org/I1339145263","display_name":"Juniper Networks (United States)","ror":"https://ror.org/02pwct569","country_code":"US","type":"company","lineage":["https://openalex.org/I1339145263"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sirisha Bhamidipathi","raw_affiliation_strings":["Juniper Networks, California, USA"],"affiliations":[{"raw_affiliation_string":"Juniper Networks, California, USA","institution_ids":["https://openalex.org/I1339145263"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5038027691"],"corresponding_institution_ids":["https://openalex.org/I4210109535"],"apc_list":null,"apc_paid":null,"fwci":1.2919,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.789763,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7864412069320679},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.7159385681152344},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.7114220857620239},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.7062762975692749},{"id":"https://openalex.org/keywords/high-level-verification","display_name":"High-level verification","score":0.5940980315208435},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5687713623046875},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5376424193382263},{"id":"https://openalex.org/keywords/verification","display_name":"Verification","score":0.4935551881790161},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.4904880225658417},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4543544054031372},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4511442184448242},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39735865592956543},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1617097556591034},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.129167377948761},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12371504306793213},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.07636997103691101}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7864412069320679},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.7159385681152344},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.7114220857620239},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.7062762975692749},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.5940980315208435},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5687713623046875},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5376424193382263},{"id":"https://openalex.org/C142284323","wikidata":"https://www.wikidata.org/wiki/Q7921323","display_name":"Verification","level":5,"score":0.4935551881790161},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.4904880225658417},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4543544054031372},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4511442184448242},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39735865592956543},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1617097556591034},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.129167377948761},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12371504306793213},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.07636997103691101},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2015.7208152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1583759903","https://openalex.org/W2139266624","https://openalex.org/W2552109100","https://openalex.org/W2962898432","https://openalex.org/W6635034717"],"related_works":["https://openalex.org/W2361881307","https://openalex.org/W2929969821","https://openalex.org/W4205300843","https://openalex.org/W2392047570","https://openalex.org/W3120172095","https://openalex.org/W3155012083","https://openalex.org/W2363848262","https://openalex.org/W2354470518","https://openalex.org/W2059150015","https://openalex.org/W2401743419"],"abstract_inverted_index":{"Hardware":[0],"IP":[1,49,79,91],"design":[2],"verification":[3,22,29,54,84],"is":[4,39],"performed":[5],"using":[6],"exhaustive":[7],"random":[8,78],"stimuli,":[9],"while":[10],"incorporating":[11],"a":[12,26,57,63,72],"coverage":[13],"driven":[14],"flow.":[15],"On":[16],"the":[17,33,36,68,82,90],"other":[18],"hand,":[19],"system-on-chip":[20],"(SoC)":[21],"methodologies,":[23],"sometimes,":[24],"use":[25],"directed":[27],"C-based":[28],"approach":[30],"to":[31,89],"validate":[32],"functionality":[34],"of":[35,48,77],"design.":[37],"There":[38],"no":[40,87],"significant":[41],"randomization":[42],"exercised":[43],"in":[44],"this":[45],"process.":[46],"Reuse":[47],"testbench":[50,92],"components":[51],"for":[52,81],"SoC":[53,83],"has":[55,61],"been":[56],"desirable":[58],"methodology,":[59],"yet":[60],"remained":[62],"challenge.":[64],"This":[65],"paper":[66],"addresses":[67],"challenge":[69],"by":[70],"proposing":[71],"flow":[73],"which":[74],"enables":[75],"reuse":[76],"stimuli":[80],"environment,":[85],"with":[86],"changes":[88],"and":[93],"testcase.":[94]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
