{"id":"https://openalex.org/W1510212589","doi":"https://doi.org/10.1109/isvdat.2015.7208151","title":"Low-leakage architecture for embedded ROM","display_name":"Low-leakage architecture for embedded ROM","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W1510212589","doi":"https://doi.org/10.1109/isvdat.2015.7208151","mag":"1510212589"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2015.7208151","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208151","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081120753","display_name":"Mansi S. Masrani","orcid":null},"institutions":[{"id":"https://openalex.org/I165831266","display_name":"Nirma University","ror":"https://ror.org/05qkq7x38","country_code":"IN","type":"education","lineage":["https://openalex.org/I165831266"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Mansi S. Masrani","raw_affiliation_strings":["Post-Graduation and Research Department, Nirma University, Ahmedabad, India","[Post-Graduation and Research Department, Nirma University, Ahmedabad, India]"],"affiliations":[{"raw_affiliation_string":"Post-Graduation and Research Department, Nirma University, Ahmedabad, India","institution_ids":["https://openalex.org/I165831266"]},{"raw_affiliation_string":"[Post-Graduation and Research Department, Nirma University, Ahmedabad, India]","institution_ids":["https://openalex.org/I165831266"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068305685","display_name":"Raghavendra Chilukuri","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Raghavendra Chilukuri","raw_affiliation_strings":["DTS CMO team, Intel Technologies India Pvt. Ltd., Bengaluru, India","[DTS CMO team, Intel Technologies India Pvt. Ltd., Bengaluru, India]"],"affiliations":[{"raw_affiliation_string":"DTS CMO team, Intel Technologies India Pvt. Ltd., Bengaluru, India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"[DTS CMO team, Intel Technologies India Pvt. Ltd., Bengaluru, India]","institution_ids":["https://openalex.org/I4210146682"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5081120753"],"corresponding_institution_ids":["https://openalex.org/I165831266"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.02108678,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6316932439804077},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.6054559946060181},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5955060720443726},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5701497197151184},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.568699836730957},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.5361276865005493},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.49242863059043884},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4575906991958618},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34047043323516846},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.33564937114715576},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2446041703224182},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.20074233412742615},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1808282732963562},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.1395288109779358}],"concepts":[{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6316932439804077},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.6054559946060181},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5955060720443726},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5701497197151184},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.568699836730957},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.5361276865005493},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.49242863059043884},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4575906991958618},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34047043323516846},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.33564937114715576},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2446041703224182},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.20074233412742615},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1808282732963562},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.1395288109779358},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2015.7208151","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208151","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5099999904632568,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W375187563","https://openalex.org/W2085555829","https://openalex.org/W6612836169"],"related_works":["https://openalex.org/W2297319780","https://openalex.org/W2178217057","https://openalex.org/W1972800815","https://openalex.org/W2550723781","https://openalex.org/W2548830639","https://openalex.org/W4252086734","https://openalex.org/W2159770326","https://openalex.org/W2078971946","https://openalex.org/W2051027227","https://openalex.org/W1505038800"],"abstract_inverted_index":{"Register":[0],"File":[1],"(RF),":[2],"Static":[3],"Random":[4],"Access":[5],"Memory":[6,11],"(SRAM)":[7],"and":[8,20,46],"Read":[9],"Only":[10],"(ROM)":[12],"arrays":[13],"on":[14,24,39],"SoCs":[15],"comprise":[16],"over":[17],"50%":[18],"area":[19],"consumes":[21],"substantial":[22],"power":[23,54,93],"die.":[25],"The":[26],"On":[27],"die":[28],"ROM":[29],"usage":[30],"is":[31,35],"increasing":[32],"as":[33,81],"there":[34],"an":[36],"increased":[37],"focus":[38],"IOTs,":[40],"multi-core":[41],"microprocessor":[42],"for":[43],"notebooks,":[44],"2-in-1s":[45],"mobile":[47],"applications.":[48],"Achieving":[49],"high":[50,77],"performance":[51,78],"at":[52],"low":[53,91],"specification":[55],"need":[56],"considerable":[57],"innovation.":[58],"Use":[59],"of":[60],"High":[61],"Threshold":[62],"Voltage":[63],"(V":[64],"<sub":[65],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[66],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">th</sub>":[67],")":[68],"devices":[69],"may":[70],"not":[71],"be":[72],"the":[73],"solution":[74],"when":[75],"targeting":[76],"designs.":[79],"Further,":[80],"technology":[82],"scales,":[83],"leakage":[84,92],"increases":[85],"exponentially,":[86],"which":[87],"requires":[88],"more":[89],"aggressive":[90],"schemes.":[94]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
