{"id":"https://openalex.org/W1577623754","doi":"https://doi.org/10.1109/isvdat.2015.7208141","title":"Standby leakage current estimation model for multi threshold CMOS inverter circuit in deep submicron technology","display_name":"Standby leakage current estimation model for multi threshold CMOS inverter circuit in deep submicron technology","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W1577623754","doi":"https://doi.org/10.1109/isvdat.2015.7208141","mag":"1577623754"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2015.7208141","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208141","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072150515","display_name":"Hari Sarkar","orcid":null},"institutions":[{"id":"https://openalex.org/I99601430","display_name":"Maulana Abul Kalam Azad University of Technology, West Bengal","ror":"https://ror.org/030tcae29","country_code":"IN","type":"education","lineage":["https://openalex.org/I99601430"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Hari Sarkar","raw_affiliation_strings":["Department of Computer Science and Engineering, West Bengal University of Technology, Kolkata, India","Dept. of Comput. Sci. & Eng., West Bengal Univ. of Technol., Kolkata, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, West Bengal University of Technology, Kolkata, India","institution_ids":["https://openalex.org/I99601430"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., West Bengal Univ. of Technol., Kolkata, India","institution_ids":["https://openalex.org/I99601430"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101095392","display_name":"Sudakshina Kundu","orcid":null},"institutions":[{"id":"https://openalex.org/I99601430","display_name":"Maulana Abul Kalam Azad University of Technology, West Bengal","ror":"https://ror.org/030tcae29","country_code":"IN","type":"education","lineage":["https://openalex.org/I99601430"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sudakshina Kundu","raw_affiliation_strings":["Department of Computer Science and Engineering, West Bengal University of Technology, Kolkata, India","Dept. of Comput. Sci. & Eng., West Bengal Univ. of Technol., Kolkata, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, West Bengal University of Technology, Kolkata, India","institution_ids":["https://openalex.org/I99601430"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., West Bengal Univ. of Technol., Kolkata, India","institution_ids":["https://openalex.org/I99601430"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5072150515"],"corresponding_institution_ids":["https://openalex.org/I99601430"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.03019782,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8033192157745361},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.7545906901359558},{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.7286828756332397},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.646636962890625},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5448723435401917},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.487239271402359},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.46935898065567017},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4518028795719147},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.43212446570396423},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.41363003849983215},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.40965431928634644},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3556831181049347},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2629980146884918}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8033192157745361},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.7545906901359558},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.7286828756332397},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.646636962890625},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5448723435401917},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.487239271402359},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.46935898065567017},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4518028795719147},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.43212446570396423},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.41363003849983215},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.40965431928634644},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3556831181049347},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2629980146884918},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2015.7208141","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208141","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6299999952316284}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W158370784","https://openalex.org/W2131862714","https://openalex.org/W6606443236"],"related_works":["https://openalex.org/W2039755656","https://openalex.org/W2900067469","https://openalex.org/W1949737515","https://openalex.org/W4253620068","https://openalex.org/W2042352336","https://openalex.org/W2130342263","https://openalex.org/W2144417859","https://openalex.org/W2147835582","https://openalex.org/W4240087758","https://openalex.org/W2043019798"],"abstract_inverted_index":{"Multi":[0],"Threshold":[1],"CMOS":[2,22,31],"(MTCMOS)":[3],"circuit":[4,82],"can":[5,51],"be":[6,52],"used":[7,39,88,96],"to":[8],"overcome":[9],"the":[10,28,41,48],"trade-off":[11],"between":[12],"speed":[13],"and":[14],"standby":[15,49,76,100],"leakage":[16,77,101],"current":[17,78,102],"inherent":[18],"in":[19,33,40,83],"single":[20],"threshold":[21,30,36],"circuit.":[23,44,107],"The":[24],"simplest":[25],"form":[26],"is":[27,59,93],"dual":[29],"(DTCMOS),":[32],"which":[34,58,92],"two":[35],"voltages":[37],"are":[38],"same":[42],"logic":[43],"As":[45],"a":[46,60,70,94],"result,":[47],"power":[50],"greatly":[53],"reduced":[54],"by":[55],"this":[56],"approach":[57],"key":[61],"factor":[62],"for":[63,72,79,99],"battery":[64],"operated":[65],"devices.":[66],"This":[67],"paper":[68],"proposed":[69],"model":[71,91,98],"analytical":[73],"calculation":[74],"of":[75,104],"MTCMOS":[80,105],"Inverter":[81,106],"90nm":[84],"technology.":[85],"We":[86],"have":[87],"BSIM":[89],"device":[90],"widely":[95],"industrial":[97],"modelling":[103]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
