{"id":"https://openalex.org/W1536543696","doi":"https://doi.org/10.1109/isvdat.2015.7208125","title":"Low power and hardware cost STUMPS BIST","display_name":"Low power and hardware cost STUMPS BIST","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W1536543696","doi":"https://doi.org/10.1109/isvdat.2015.7208125","mag":"1536543696"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2015.7208125","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208125","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109343809","display_name":"N. Ravi Kiran","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"N Ravi Kiran","raw_affiliation_strings":["VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028258971","display_name":"G. Harish","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"G Harish","raw_affiliation_strings":["VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001307119","display_name":"A. Karthik","orcid":"https://orcid.org/0000-0002-7354-4485"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A Karthik","raw_affiliation_strings":["VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076480907","display_name":"Siva Yellampalli","orcid":"https://orcid.org/0000-0001-6774-1514"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Siva Yellampalli","raw_affiliation_strings":["VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6589,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.67711572,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9954000115394592,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7363776564598083},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7000393867492676},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.6693204641342163},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6236960887908936},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5296026468276978},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4934348165988922},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.49063459038734436},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.41025733947753906},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.4037695527076721},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3832945227622986},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3399851322174072},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.26621997356414795},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.23471006751060486}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7363776564598083},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7000393867492676},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.6693204641342163},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6236960887908936},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5296026468276978},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4934348165988922},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.49063459038734436},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.41025733947753906},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4037695527076721},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3832945227622986},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3399851322174072},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.26621997356414795},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.23471006751060486},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2015.7208125","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208125","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W53227076","https://openalex.org/W197391467","https://openalex.org/W2082581734","https://openalex.org/W2135627440","https://openalex.org/W2548411222","https://openalex.org/W3203992401","https://openalex.org/W6602153322","https://openalex.org/W6607990715","https://openalex.org/W6656594533"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2164493372","https://openalex.org/W2114980936","https://openalex.org/W2150046587","https://openalex.org/W2142405811","https://openalex.org/W1594445436","https://openalex.org/W4245595174","https://openalex.org/W2115513740","https://openalex.org/W2539511314"],"abstract_inverted_index":{"Traditionally":[0],"BIST":[1,19,46,82,98],"is":[2,47,83],"most":[3],"widely":[4],"used":[5,76],"testing":[6,15],"methodology":[7],"because":[8],"of":[9,28,53,61,70],"its":[10],"online":[11],"and":[12,37,66,90,107],"at":[13],"speed":[14],"capability.":[16],"The":[17,80],"conventional":[18],"suffers":[20],"from":[21],"hardware":[22,44],"overhead":[23,103,109],"due":[24],"to":[25],"the":[26,51,58,68,91,96,101],"presence":[27],"on-chip":[29],"test":[30],"blocks":[31],"such":[32],"as":[33,64],"TPG,":[34],"MISR,":[35],"ROM":[36],"ORA.":[38],"In":[39],"this":[40],"paper":[41],"a":[42],"low":[43],"cost":[45],"proposed,":[48],"which":[49],"eliminates":[50],"requirement":[52],"external":[54],"TPG":[55,65],"by":[56,104,110],"reconfiguring":[57],"first":[59],"flops":[60,75],"scan":[62],"chains":[63],"ensures":[67],"testability":[69],"combinational":[71],"logic":[72],"present":[73],"between":[74],"for":[77],"constructing":[78],"LFSR.":[79],"proposed":[81,97],"tested":[84],"with":[85],"standard":[86],"ISCAS'89":[87],"benchmark":[88],"circuits":[89],"experimental":[92],"results":[93],"shows":[94],"that":[95],"averagely":[99],"reduces":[100],"area":[102],"25.6":[105],"%":[106],"power":[108],"22.3":[111],"%.":[112]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2017,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}