{"id":"https://openalex.org/W1559376383","doi":"https://doi.org/10.1109/isvdat.2015.7208117","title":"RISC-V out-of-order data conversion co-processor","display_name":"RISC-V out-of-order data conversion co-processor","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W1559376383","doi":"https://doi.org/10.1109/isvdat.2015.7208117","mag":"1559376383"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2015.7208117","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208117","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022564712","display_name":"Aneesh Raveendran","orcid":null},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Aneesh Raveendran","raw_affiliation_strings":["Centre for Development of Advanced Computing, Bangalore, INDIA","Centre for Development of Advanced Computing Bangalore India"],"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing, Bangalore, INDIA","institution_ids":["https://openalex.org/I1331500379"]},{"raw_affiliation_string":"Centre for Development of Advanced Computing Bangalore India","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036850130","display_name":"Vinayak Patil","orcid":null},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vinayak Patil","raw_affiliation_strings":["Centre for Development of Advanced Computing, Bangalore, INDIA","Centre for Development of Advanced Computing Bangalore India"],"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing, Bangalore, INDIA","institution_ids":["https://openalex.org/I1331500379"]},{"raw_affiliation_string":"Centre for Development of Advanced Computing Bangalore India","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028262376","display_name":"Vivian Desalphine","orcid":null},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vivian Desalphine","raw_affiliation_strings":["Centre for Development of Advanced Computing, Bangalore, INDIA","Centre for Development of Advanced Computing Bangalore India"],"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing, Bangalore, INDIA","institution_ids":["https://openalex.org/I1331500379"]},{"raw_affiliation_string":"Centre for Development of Advanced Computing Bangalore India","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032649535","display_name":"P M Sobha","orcid":null},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P M Sobha","raw_affiliation_strings":["Centre for Development of Advanced Computing, Juhu, Maharashtra, IN","Centre for Development of Advanced Computing Bangalore India"],"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing, Juhu, Maharashtra, IN","institution_ids":[]},{"raw_affiliation_string":"Centre for Development of Advanced Computing Bangalore India","institution_ids":["https://openalex.org/I1331500379"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001173788","display_name":"Anith Selvakumar","orcid":null},"institutions":[{"id":"https://openalex.org/I1331500379","display_name":"Centre for Development of Advanced Computing","ror":"https://ror.org/022abst40","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1331500379","https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A David Selvakumar","raw_affiliation_strings":["Centre for Development of Advanced Computing, Bangalore, INDIA","Centre for Development of Advanced Computing Bangalore India"],"affiliations":[{"raw_affiliation_string":"Centre for Development of Advanced Computing, Bangalore, INDIA","institution_ids":["https://openalex.org/I1331500379"]},{"raw_affiliation_string":"Centre for Development of Advanced Computing Bangalore India","institution_ids":["https://openalex.org/I1331500379"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5022564712"],"corresponding_institution_ids":["https://openalex.org/I1331500379"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.02863451,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.98580002784729,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.98580002784729,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9854999780654907,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9765999913215637,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8083878755569458},{"id":"https://openalex.org/keywords/floating-point-unit","display_name":"Floating-point unit","score":0.7158858776092529},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.6862308382987976},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.6827071905136108},{"id":"https://openalex.org/keywords/out-of-order-execution","display_name":"Out-of-order execution","score":0.6207671165466309},{"id":"https://openalex.org/keywords/double-precision-floating-point-format","display_name":"Double-precision floating-point format","score":0.5983112454414368},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5803055763244629},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5548025965690613},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.5514876246452332},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.541762113571167},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.514998197555542},{"id":"https://openalex.org/keywords/data-conversion","display_name":"Data conversion","score":0.476392924785614},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.464780330657959},{"id":"https://openalex.org/keywords/instructions-per-cycle","display_name":"Instructions per cycle","score":0.4379960298538208},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3970661759376526},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2887420356273651},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.22361722588539124},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.12876373529434204}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8083878755569458},{"id":"https://openalex.org/C110305270","wikidata":"https://www.wikidata.org/wiki/Q733507","display_name":"Floating-point unit","level":3,"score":0.7158858776092529},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.6862308382987976},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.6827071905136108},{"id":"https://openalex.org/C1793878","wikidata":"https://www.wikidata.org/wiki/Q1153762","display_name":"Out-of-order execution","level":2,"score":0.6207671165466309},{"id":"https://openalex.org/C35912277","wikidata":"https://www.wikidata.org/wiki/Q1243369","display_name":"Double-precision floating-point format","level":3,"score":0.5983112454414368},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5803055763244629},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5548025965690613},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.5514876246452332},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.541762113571167},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.514998197555542},{"id":"https://openalex.org/C1232282","wikidata":"https://www.wikidata.org/wiki/Q1783551","display_name":"Data conversion","level":2,"score":0.476392924785614},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.464780330657959},{"id":"https://openalex.org/C156972235","wikidata":"https://www.wikidata.org/wiki/Q1443434","display_name":"Instructions per cycle","level":3,"score":0.4379960298538208},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3970661759376526},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2887420356273651},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.22361722588539124},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.12876373529434204},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2015.7208117","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208117","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6700000166893005,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W6987144925"],"related_works":["https://openalex.org/W1559376383","https://openalex.org/W4389476319","https://openalex.org/W2141421298","https://openalex.org/W2146655423","https://openalex.org/W2169029159","https://openalex.org/W2364912196","https://openalex.org/W1485761350","https://openalex.org/W2065030266","https://openalex.org/W563794549","https://openalex.org/W1680705574"],"abstract_inverted_index":{"Data":[0],"conversion":[1,19,77,98,104,109,118,132,160,175,221,231,260],"operations":[2,65],"are":[3,66],"important":[4],"and":[5,15,27,35,46,56,60,71,140,151,168,186,238,246],"essential":[6],"part":[7,67,81],"of":[8,68,82,136,157,190,257],"floating":[9,25,30,130,143,192,206],"point":[10,26,31,34,108,131,144,193,207],"units":[11],"in":[12,88,147],"a":[13],"processor":[14,161],"typical":[16],"instructions":[17,43,119],"include":[18],"between":[20,53],"various":[21],"precisions,":[22],"integer":[23,224],"to":[24,32,44],"vice":[28,36,61],"versa,":[29],"fixed":[33],"versa":[37,62],"etc.":[38,63,73],"Besides":[39],"few":[40],"processors":[41],"have":[42,264],"round":[45],"truncate":[47],"data,":[48],"sign":[49],"injections,":[50],"move":[51],"data":[52,97,103,117,145,159,164,220,230],"co-processors":[54],"registers":[55,59],"general":[57],"purpose":[58],"Conversion":[64],"ARM,":[69],"MIPS,":[70],"RISC-V":[72,101,116,214],"instruction":[74,181,215],"sets.":[75],"The":[76,106,129,154,188,217,226],"functionalities":[78],"can":[79],"be":[80,86],"hardware":[83],"or":[84,200],"may":[85],"implemented":[87],"software.":[89],"This":[90],"paper":[91],"details":[92],"an":[93,180],"architectural":[94],"exploration":[95],"for":[96,100,149,172,183,219,229],"coprocessor":[99],"[1]":[102],"instructions.":[105],"Floating":[107],"unit":[110,194],"that":[111],"has":[112,242],"been":[113,243,265],"designed":[114],"with":[115,123,179,197,205,223,233],"is":[120,134,177,195],"fully":[121],"compatible":[122],"IEEE":[124],"754-2008":[125],"standard":[126],"as":[127],"well.":[128],"co-processor":[133,218,232],"capable":[135],"handling":[137],"both":[138],"single":[139,199],"double":[141,201],"precision":[142,202],"operands":[146],"out-of-order":[148,234],"execution":[150],"in-order":[152,184,236],"commit.":[153,187],"front":[155],"end":[156],"the":[158,191,213],"accepts":[162],"three":[163],"operands,":[165],"rounding":[166],"mode":[167],"associated":[169],"Op-code":[170],"fields":[171],"decoding.":[173],"Each":[174],"operation":[176],"tagged":[178,196],"token":[182],"completion":[185,239],"output":[189],"either":[198],"results":[203],"along":[204],"exceptions":[208],"if":[209],"any,":[210],"based":[211],"on":[212,248],"set.":[216],"integrates":[222],"pipeline.":[225],"proposed":[227],"architecture":[228],"execution,":[235],"commit":[237],"/":[240],"retire":[241],"synthesized,":[244],"tested":[245],"verified":[247],"Xilinx":[249],"Virtex":[250],"6":[251],"xc6vlx550t-2ff1759":[252],"FPGA.":[253],"A":[254],"performance":[255],"throughput":[256],"350MFLOPs":[258],"(data":[259],"operations)":[261],"per":[262],"second":[263],"observed.":[266]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
