{"id":"https://openalex.org/W1585999621","doi":"https://doi.org/10.1109/isvdat.2015.7208082","title":"An offset-tolerant self-correcting sense amplifier for robust high speed SRAM","display_name":"An offset-tolerant self-correcting sense amplifier for robust high speed SRAM","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W1585999621","doi":"https://doi.org/10.1109/isvdat.2015.7208082","mag":"1585999621"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2015.7208082","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208082","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111462475","display_name":"Praneet Bhatia","orcid":null},"institutions":[{"id":"https://openalex.org/I74796645","display_name":"Birla Institute of Technology and Science, Pilani","ror":"https://ror.org/001p3jz28","country_code":"IN","type":"education","lineage":["https://openalex.org/I74796645"]},{"id":"https://openalex.org/I4210148827","display_name":"Birla Institute of Technology and Science, Pilani - Goa Campus","ror":"https://ror.org/046sh6j17","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210148827","https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Praneet Bhatia","raw_affiliation_strings":["BITS Pilani K.K. Birla Goa Campus","Bits Pilani K K Birla Goa Campus"],"affiliations":[{"raw_affiliation_string":"BITS Pilani K.K. Birla Goa Campus","institution_ids":["https://openalex.org/I4210148827"]},{"raw_affiliation_string":"Bits Pilani K K Birla Goa Campus","institution_ids":["https://openalex.org/I74796645"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050869066","display_name":"Bhupendra Singh Reniwal","orcid":"https://orcid.org/0000-0002-5586-5365"},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"B. S. Reniwal","raw_affiliation_strings":["Nanoscale Devices, Indian Institute of Technology, Indore, India","Nanoscale Devices, VLSI Circuit & System Design Lab, Department of Electrical Engineering; Indian Institute of Technology; Indore India"],"affiliations":[{"raw_affiliation_string":"Nanoscale Devices, Indian Institute of Technology, Indore, India","institution_ids":["https://openalex.org/I64295750"]},{"raw_affiliation_string":"Nanoscale Devices, VLSI Circuit & System Design Lab, Department of Electrical Engineering; Indian Institute of Technology; Indore India","institution_ids":["https://openalex.org/I64295750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068792760","display_name":"Santosh Kumar Vishvakarma","orcid":"https://orcid.org/0000-0003-4223-0077"},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. K. Vishvakarma","raw_affiliation_strings":["Nanoscale Devices, Indian Institute of Technology, Indore, India","Nanoscale Devices, VLSI Circuit & System Design Lab, Department of Electrical Engineering; Indian Institute of Technology; Indore India"],"affiliations":[{"raw_affiliation_string":"Nanoscale Devices, Indian Institute of Technology, Indore, India","institution_ids":["https://openalex.org/I64295750"]},{"raw_affiliation_string":"Nanoscale Devices, VLSI Circuit & System Design Lab, Department of Electrical Engineering; Indian Institute of Technology; Indore India","institution_ids":["https://openalex.org/I64295750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5111462475"],"corresponding_institution_ids":["https://openalex.org/I4210148827","https://openalex.org/I74796645"],"apc_list":null,"apc_paid":null,"fwci":0.7891,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.75204462,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.7672675848007202},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.6988227963447571},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.6077781915664673},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5959978103637695},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5291975736618042},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5127604603767395},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.4929830729961395},{"id":"https://openalex.org/keywords/input-offset-voltage","display_name":"Input offset voltage","score":0.471921443939209},{"id":"https://openalex.org/keywords/sense","display_name":"Sense (electronics)","score":0.4460664987564087},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.43289411067962646},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4328681230545044},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.41760823130607605},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4002389907836914},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3060828447341919},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2810085415840149},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.2342800498008728},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18049746751785278},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.09641286730766296}],"concepts":[{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.7672675848007202},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.6988227963447571},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.6077781915664673},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5959978103637695},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5291975736618042},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5127604603767395},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.4929830729961395},{"id":"https://openalex.org/C63651839","wikidata":"https://www.wikidata.org/wiki/Q478566","display_name":"Input offset voltage","level":5,"score":0.471921443939209},{"id":"https://openalex.org/C143141573","wikidata":"https://www.wikidata.org/wiki/Q7450971","display_name":"Sense (electronics)","level":2,"score":0.4460664987564087},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.43289411067962646},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4328681230545044},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.41760823130607605},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4002389907836914},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3060828447341919},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2810085415840149},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.2342800498008728},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18049746751785278},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.09641286730766296},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2015.7208082","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208082","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7200000286102295,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1967035245","https://openalex.org/W1970598944","https://openalex.org/W2028643888","https://openalex.org/W2029924700","https://openalex.org/W2046515116","https://openalex.org/W2092277707","https://openalex.org/W2100094882","https://openalex.org/W2105614673","https://openalex.org/W2115376510","https://openalex.org/W2119426820","https://openalex.org/W2122435992","https://openalex.org/W2139138351","https://openalex.org/W2140823559","https://openalex.org/W2150460978","https://openalex.org/W2164967515","https://openalex.org/W2165716336","https://openalex.org/W2545471485"],"related_works":["https://openalex.org/W1835913819","https://openalex.org/W2051363901","https://openalex.org/W2029990318","https://openalex.org/W2601845499","https://openalex.org/W2127348582","https://openalex.org/W2117344730","https://openalex.org/W4231592364","https://openalex.org/W3085306935","https://openalex.org/W2373152541","https://openalex.org/W4288047258"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"have":[4],"proposed":[5],"a":[6,39,46,68,121,131],"novel":[7],"Sense":[8,71,80],"Amplifier":[9,72,81],"(SA)":[10],"design":[11,65],"which":[12,29],"is":[13,66],"capable":[14],"of":[15,19],"predetermining":[16],"the":[17,25,50,55,64],"direction":[18],"offset":[20,87,116],"in":[21,24,45,89,115,120,124],"threshold":[22],"voltage":[23],"sensing":[26,113],"transistors":[27],"and":[28,83,109,135,140],"provides":[30],"up":[31],"to":[32,43,49,59,93],"24%":[33],"more":[34],"current":[35,42],"differential":[36],"by":[37],"activating":[38],"path":[40],"for":[41],"flow":[44],"device,":[47],"parallel":[48],"weaker":[51],"transistor,":[52],"thus":[53,129],"compensating":[54],"inherent":[56],"offset.":[57],"Due":[58],"its":[60],"self":[61],"correcting":[62],"capability,":[63],"called":[67],"Self":[69],"Correcting":[70],"(SCSA).":[73],"Analysis":[74],"carried":[75],"out":[76],"on":[77],"Current":[78],"Latch":[79],"(CLSA)":[82],"SCSA":[84,90,102],"showed":[85],"2.3\u00d7":[86],"tolerance":[88],"when":[91],"compared":[92],"CLSA":[94],"at":[95],"high-density":[96],"SRAM":[97],"conditions":[98],"(500fF":[99],"bit-line":[100,141],"capacitance).":[101],"also":[103],"consumed":[104],"9%":[105],"less":[106,112],"dynamic":[107],"power":[108,125],"offers":[110,130],"13%":[111],"delay":[114,126],"condition.":[117],"This":[118],"resulted":[119],"27%":[122],"reduction":[123],"product.":[127],"It":[128],"much":[132],"better":[133],"read-effectiveness":[134],"robustness":[136],"against":[137],"device":[138],"mismatch":[139],"capacitances":[142],"as":[143,145],"well":[144],"V":[146],"<sub":[147],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[148],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">DD</sub>":[149],"variation.":[150]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}