{"id":"https://openalex.org/W4235829465","doi":"https://doi.org/10.1109/isvdat.2015.7208074","title":"Implementation of high speed radix-10 parallel multiplier using Verilog","display_name":"Implementation of high speed radix-10 parallel multiplier using Verilog","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W4235829465","doi":"https://doi.org/10.1109/isvdat.2015.7208074"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2015.7208074","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208074","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090187030","display_name":"Sonam Negi","orcid":null},"institutions":[{"id":"https://openalex.org/I60054993","display_name":"Graphic Era University","ror":"https://ror.org/03wqgqd89","country_code":"IN","type":"education","lineage":["https://openalex.org/I60054993"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Sonam Negi","raw_affiliation_strings":["Dept. of ECE, Graphic Era University, Dehradun, India"],"affiliations":[{"raw_affiliation_string":"Dept. of ECE, Graphic Era University, Dehradun, India","institution_ids":["https://openalex.org/I60054993"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026252528","display_name":"Pitchaiah Madduri","orcid":null},"institutions":[{"id":"https://openalex.org/I60054993","display_name":"Graphic Era University","ror":"https://ror.org/03wqgqd89","country_code":"IN","type":"education","lineage":["https://openalex.org/I60054993"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pitchaiah Madduri","raw_affiliation_strings":["Dept. of ECE, Graphic Era University, Dehradun, India"],"affiliations":[{"raw_affiliation_string":"Dept. of ECE, Graphic Era University, Dehradun, India","institution_ids":["https://openalex.org/I60054993"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5090187030"],"corresponding_institution_ids":["https://openalex.org/I60054993"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.31609991,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8095639944076538},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7295645475387573},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.694133996963501},{"id":"https://openalex.org/keywords/multiplication","display_name":"Multiplication (music)","score":0.6684648394584656},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.6462603211402893},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6415594220161438},{"id":"https://openalex.org/keywords/multiplication-algorithm","display_name":"Multiplication algorithm","score":0.5306041836738586},{"id":"https://openalex.org/keywords/booths-multiplication-algorithm","display_name":"Booth's multiplication algorithm","score":0.4838048815727234},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4343148469924927},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36031362414360046},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.30107879638671875},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.20965152978897095},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.2057853639125824},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.0813153088092804}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8095639944076538},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7295645475387573},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.694133996963501},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.6684648394584656},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.6462603211402893},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6415594220161438},{"id":"https://openalex.org/C201290732","wikidata":"https://www.wikidata.org/wiki/Q130762","display_name":"Multiplication algorithm","level":3,"score":0.5306041836738586},{"id":"https://openalex.org/C72475854","wikidata":"https://www.wikidata.org/wiki/Q477049","display_name":"Booth's multiplication algorithm","level":4,"score":0.4838048815727234},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4343148469924927},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36031362414360046},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.30107879638671875},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.20965152978897095},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.2057853639125824},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0813153088092804},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2015.7208074","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208074","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6499999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1986780368","https://openalex.org/W2110538940","https://openalex.org/W2121202037","https://openalex.org/W2125266075","https://openalex.org/W2133140834","https://openalex.org/W2142454275","https://openalex.org/W2146871557","https://openalex.org/W2154098572","https://openalex.org/W2169559417","https://openalex.org/W2547482522","https://openalex.org/W3047533065","https://openalex.org/W6781234328"],"related_works":["https://openalex.org/W2171373222","https://openalex.org/W4312097652","https://openalex.org/W2377156450","https://openalex.org/W4281629491","https://openalex.org/W3138499576","https://openalex.org/W2158685723","https://openalex.org/W2546612563","https://openalex.org/W2352033875","https://openalex.org/W2370292629","https://openalex.org/W2086473731"],"abstract_inverted_index":{"The":[0,11,55,88,143,195,221],"emerging":[1],"computational":[2],"complexities":[3],"arises":[4],"the":[5,27,38,49,101,134,159,163,184,189,199,205,213,260,267,282],"need":[6],"of":[7,13,40,57,162,169,191,207,217,262,273],"fast":[8],"multiplication":[9,14,28,174,219,290],"unit.":[10,220],"importance":[12],"in":[15,20,83,158,226,253,259,266,281],"various":[16],"applications":[17,71],"necessitates":[18],"improvement":[19],"its":[21],"design":[22,214,222],"so":[23],"as":[24,82,124],"to":[25,43,104,106,110,121,130,287],"obtain":[26],"result":[29],"efficiently.":[30],"Multiplication":[31],"operation":[32],"can":[33,60],"be":[34,44,61,131],"improved":[35],"by":[36,47,63],"reducing":[37,204],"number":[39,56,261],"partial":[41,58,170],"products":[42,59],"added":[45],"and":[46,112,133,166,215,232,240,256],"enhancing":[48],"adder":[50,179],"unit":[51],"for":[52,291],"obtaining":[53],"sum.":[54],"reduced":[62],"using":[64,93,139,234,242],"higher":[65],"radix":[66],"multiplication.":[67],"For":[68],"better":[69],"speed":[70,289],"a":[72,115],"radix-10":[73,97],"multiplier":[74,80,86,89],"is":[75,151,156,180,224,238,264,278],"proposed":[76],"which":[77,99,182],"uses":[78],"recoded":[79],"digits":[81,90],"conventional":[84],"parallel":[85],"design.":[87],"are":[91,128,137,146],"encoded":[92],"Signed":[94],"Digit":[95],"(SD)":[96],"method":[98],"converts":[100],"digit":[102,165],"set":[103],"{-5":[105],"5}":[107],"from":[108],"{0":[109],"9}":[111],"also":[113,279],"generate":[114],"sign":[116,149],"bit.":[117],"This":[118,210],"recoding":[119,201],"leads":[120],"minimized":[122],"calculations":[123],"only":[125],"five":[126],"multiples":[127,136,145,160],"required":[129],"calculated":[132],"negative":[135,144],"obtained":[138,172],"2's":[140],"complement":[141],"approach.":[142],"used":[147,181],"when":[148],"bit":[150],"high.":[152],"A":[153,176],"different":[154],"approach":[155],"availed":[157],"generation":[161],"multiplicand":[164],"during":[167,173],"accumulation":[168],"product":[171],"procedure.":[175],"modified":[177,196,268,283],"BCD":[178,193],"eliminates":[183,198],"post":[185],"correction":[186],"while":[187],"calculating":[188],"sum":[190],"two":[192],"digits.":[194],"architecture":[197],"extra":[200],"logic":[202],"thereby":[203,285],"area":[206],"overall":[208],"architecture.":[209],"paper":[211],"delivers":[212],"implementation":[216],"16-Bit":[218],"entry":[223],"done":[225],"Verilog":[227],"Hardware":[228],"Description":[229],"Language":[230],"(HDL)":[231],"simulated":[233],"ISIM":[235],"Simulator.":[236],"It":[237],"synthesized":[239],"implemented":[241],"Xilinx":[243],"ISE":[244],"12.2.":[245],"Synthesis":[246],"results":[247],"have":[248],"shown":[249],"that":[250],"20.3%":[251],"reduction":[252,258,272],"4-Input":[254],"LUTs":[255],"20.4%":[257],"slices":[263],"observed":[265,280],"methodology.":[269],"Further":[270],"11.5%":[271],"maximum":[274],"combinational":[275],"path":[276],"delay":[277],"architecture,":[284],"leading":[286],"high":[288],"VLSI":[292],"applications.":[293]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}