{"id":"https://openalex.org/W4252202719","doi":"https://doi.org/10.1109/isss.1999.814267","title":"Efficient scheduling of DSP code on processors with distributed register files","display_name":"Efficient scheduling of DSP code on processors with distributed register files","publication_year":2003,"publication_date":"2003-01-20","ids":{"openalex":"https://openalex.org/W4252202719","doi":"https://doi.org/10.1109/isss.1999.814267"},"language":"en","primary_location":{"id":"doi:10.1109/isss.1999.814267","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isss.1999.814267","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 12th International Symposium on System Synthesis","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011378033","display_name":"Bart Mesman","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122849","display_name":"Philips (Netherlands)","ror":"https://ror.org/02p2bgp27","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210122849"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"B. Mesman","raw_affiliation_strings":["Philips Research Laboratories, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"Philips Research Laboratories, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I4210122849"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091731863","display_name":"C.A. Alba Pinto","orcid":null},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"C.A. Alba Pinto","raw_affiliation_strings":["Department of Electrical Engineering, Eindhovan University of Technology, Netherlands"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Eindhovan University of Technology, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055515050","display_name":"K. van Eijk","orcid":null},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"K. van Eijk","raw_affiliation_strings":["Department of Electrical Engineering, Eindhovan University of Technology, Netherlands"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Eindhovan University of Technology, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5011378033"],"corresponding_institution_ids":["https://openalex.org/I4210122849"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.40613736,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"100","last_page":"106"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8430022597312927},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.7247611284255981},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.7221802473068237},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6660253405570984},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5820660591125488},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.5712509155273438},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5376054048538208},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.4348139762878418},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.42188698053359985},{"id":"https://openalex.org/keywords/processor-scheduling","display_name":"Processor scheduling","score":0.4138023853302002},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.2568793296813965},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.21699723601341248},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.21666491031646729},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18013861775398254},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.16414323449134827},{"id":"https://openalex.org/keywords/two-level-scheduling","display_name":"Two-level scheduling","score":0.137398362159729},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11868083477020264},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.062035441398620605}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8430022597312927},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.7247611284255981},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.7221802473068237},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6660253405570984},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5820660591125488},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.5712509155273438},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5376054048538208},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.4348139762878418},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.42188698053359985},{"id":"https://openalex.org/C2984822820","wikidata":"https://www.wikidata.org/wiki/Q1123036","display_name":"Processor scheduling","level":3,"score":0.4138023853302002},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.2568793296813965},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.21699723601341248},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.21666491031646729},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18013861775398254},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.16414323449134827},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.137398362159729},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11868083477020264},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.062035441398620605},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isss.1999.814267","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isss.1999.814267","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 12th International Symposium on System Synthesis","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6399999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W82951293","https://openalex.org/W2118866757","https://openalex.org/W2166203884","https://openalex.org/W2539144973","https://openalex.org/W2752885492","https://openalex.org/W4232919122","https://openalex.org/W4234195212","https://openalex.org/W4235153179","https://openalex.org/W4242256571","https://openalex.org/W6676990645"],"related_works":["https://openalex.org/W2165125411","https://openalex.org/W3022691489","https://openalex.org/W2581286023","https://openalex.org/W2104554143","https://openalex.org/W2554856125","https://openalex.org/W2000718530","https://openalex.org/W4240994858","https://openalex.org/W2054117411","https://openalex.org/W1506246762","https://openalex.org/W2161016424"],"abstract_inverted_index":{"Code":[0],"generation":[1],"methods":[2,31],"for":[3,95],"digital":[4],"signal":[5],"processors":[6],"are":[7,68,74],"increasingly":[8],"hampered":[9],"by":[10,18],"the":[11,19,22,26,43,50,53,83],"combination":[12,54],"of":[13,25,55,98],"tight":[14],"timing":[15,44,62],"constraints":[16,63,73],"imposed":[17],"algorithms":[20],"and":[21,61],"limited":[23,56],"capacity":[24,39,72],"available":[27],"register":[28,57],"files.":[29],"Traditional":[30],"that":[32,87],"schedule":[33],"spill":[34],"code":[35],"to":[36,76],"satisfy":[37],"storage":[38],"have":[40],"difficulty":[41],"satisfying":[42],"constraints.":[45],"The":[46],"method":[47],"presented":[48],"in":[49,82],"paper":[51],"analyses":[52],"file":[58],"capacity,":[59],"resource-":[60],"during":[64],"scheduling.":[65,80],"Value":[66],"lifetimes":[67],"serialized":[69],"until":[70],"all":[71],"guaranteed":[75],"be":[77],"satisfied":[78],"after":[79],"Experiments":[81],"FACTS":[84],"environment":[85],"show":[86],"we":[88],"efficiently":[89],"obtain":[90],"high":[91],"quality":[92],"instruction":[93],"schedules":[94],"innermost":[96],"loops":[97],"DSP":[99],"algorithms.":[100]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}