{"id":"https://openalex.org/W2916027198","doi":"https://doi.org/10.1109/isspit.2018.8642667","title":"Behavioral Implementation of SVD on FPGA","display_name":"Behavioral Implementation of SVD on FPGA","publication_year":2018,"publication_date":"2018-12-01","ids":{"openalex":"https://openalex.org/W2916027198","doi":"https://doi.org/10.1109/isspit.2018.8642667","mag":"2916027198"},"language":"en","primary_location":{"id":"doi:10.1109/isspit.2018.8642667","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isspit.2018.8642667","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083896454","display_name":"Mi Tian","orcid":null},"institutions":[{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Mi TIAN","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Victoria, British Columbia, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Victoria, British Columbia, Canada","institution_ids":["https://openalex.org/I212119943"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057365306","display_name":"Mihai Sima","orcid":"https://orcid.org/0000-0002-1945-5190"},"institutions":[{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mihai SIMA","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Victoria, British Columbia, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Victoria, British Columbia, Canada","institution_ids":["https://openalex.org/I212119943"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072436975","display_name":"Michael McGuire","orcid":"https://orcid.org/0000-0001-7343-959X"},"institutions":[{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Michael McGUIRE","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Victoria, British Columbia, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Victoria, British Columbia, Canada","institution_ids":["https://openalex.org/I212119943"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5083896454"],"corresponding_institution_ids":["https://openalex.org/I212119943"],"apc_list":null,"apc_paid":null,"fwci":0.6058,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.72321464,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"495","last_page":"500"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9220449924468994},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.772098183631897},{"id":"https://openalex.org/keywords/singular-value-decomposition","display_name":"Singular value decomposition","score":0.6805620789527893},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.5738292932510376},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5576062798500061},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.5435559153556824},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5154062509536743},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4848662316799164},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4669766426086426},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.43181371688842773},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.42110562324523926},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4084629416465759},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3611988425254822},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1173064112663269}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9220449924468994},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.772098183631897},{"id":"https://openalex.org/C22789450","wikidata":"https://www.wikidata.org/wiki/Q420904","display_name":"Singular value decomposition","level":2,"score":0.6805620789527893},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.5738292932510376},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5576062798500061},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.5435559153556824},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5154062509536743},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4848662316799164},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4669766426086426},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.43181371688842773},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.42110562324523926},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4084629416465759},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3611988425254822},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1173064112663269},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isspit.2018.8642667","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isspit.2018.8642667","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.49000000953674316,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1525760131","https://openalex.org/W1554369651","https://openalex.org/W1574919781","https://openalex.org/W1790329066","https://openalex.org/W1861217351","https://openalex.org/W1938562002","https://openalex.org/W1970609343","https://openalex.org/W1985956780","https://openalex.org/W2017192372","https://openalex.org/W2058251587","https://openalex.org/W2061052657","https://openalex.org/W2089243291","https://openalex.org/W2092855040","https://openalex.org/W2093637157","https://openalex.org/W2102649326","https://openalex.org/W2111241284","https://openalex.org/W2115452265","https://openalex.org/W2117391305","https://openalex.org/W2127871910","https://openalex.org/W2136000919","https://openalex.org/W2169512887","https://openalex.org/W2504777671","https://openalex.org/W2572346824","https://openalex.org/W2587226214","https://openalex.org/W2600182782","https://openalex.org/W4241812161","https://openalex.org/W6675535285"],"related_works":["https://openalex.org/W2075931580","https://openalex.org/W2112121923","https://openalex.org/W2806213018","https://openalex.org/W1982150706","https://openalex.org/W2158082586","https://openalex.org/W2359192593","https://openalex.org/W2120461351","https://openalex.org/W4240991951","https://openalex.org/W2038293309","https://openalex.org/W2159978976"],"abstract_inverted_index":{"Implementing":[0],"Singular-Value":[1],"Decomposition":[2],"(SVD)":[3],"in":[4,10,90],"real":[5],"time":[6],"is":[7,27,47],"a":[8,20,35,62],"requirement":[9],"wireless":[11],"communications.":[12],"Pure-software":[13],"solutions":[14],"are":[15,89],"not":[16],"likely":[17],"to":[18,38,60],"provide":[19,34],"satisfactory":[21],"computing":[22,84],"speed;":[23],"thus,":[24],"hardware":[25,40,87],"support":[26],"needed.":[28],"Field-Programmable":[29],"Gate":[30],"Arrays":[31],"(FPGA)":[32],"can":[33,68],"cost-effective":[36],"alternative":[37],"full-custom":[39],"as":[41,43],"long":[42],"the":[44,50,76,79],"digital":[45],"design":[46,80],"tuned":[48],"toward":[49],"specific":[51],"reconfigurable":[52],"architecture.":[53],"In":[54],"this":[55],"paper,":[56],"we":[57],"describe":[58],"techniques":[59],"generate":[61],"behavioral":[63],"implementation":[64],"of":[65,78],"SVD":[66],"that":[67],"be":[69],"mapped":[70],"easily":[71],"onto":[72],"FPGA,":[73],"thereby":[74],"reducing":[75],"effort":[77],"and":[81,86],"coding.":[82],"The":[83],"performance":[85],"complexity":[88],"line":[91],"or":[92],"better":[93],"than":[94],"prior-art.":[95]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
