{"id":"https://openalex.org/W2053537812","doi":"https://doi.org/10.1109/issoc.2013.6675263","title":"A cycle accurate simulation framework for asynchronous NoC design","display_name":"A cycle accurate simulation framework for asynchronous NoC design","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W2053537812","doi":"https://doi.org/10.1109/issoc.2013.6675263","mag":"2053537812"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2013.6675263","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2013.6675263","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056526531","display_name":"Federico Terraneo","orcid":"https://orcid.org/0000-0001-7475-6167"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Federico Terraneo","raw_affiliation_strings":["DEIB - Politecnico di Milano, Milano, ITALY","DEIB, Politec. di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"DEIB - Politecnico di Milano, Milano, ITALY","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"DEIB, Politec. di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016373122","display_name":"Davide Zoni","orcid":"https://orcid.org/0000-0002-9951-062X"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Zoni","raw_affiliation_strings":["DEIB - Politecnico di Milano, Milano, ITALY","DEIB, Politec. di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"DEIB - Politecnico di Milano, Milano, ITALY","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"DEIB, Politec. di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052803987","display_name":"William Fornaciari","orcid":"https://orcid.org/0000-0001-8294-730X"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"William Fornaciari","raw_affiliation_strings":["DEIB - Politecnico di Milano, Milano, ITALY","DEIB, Politec. di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"DEIB - Politecnico di Milano, Milano, ITALY","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"DEIB, Politec. di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5056526531"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":1.8123,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.86915692,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8267471790313721},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7690349817276001},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.7582853436470032},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7564013004302979},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.52562016248703},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4970104992389679},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4846280515193939},{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"Frequency scaling","score":0.4348289966583252},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4283599853515625},{"id":"https://openalex.org/keywords/obstacle","display_name":"Obstacle","score":0.42794832587242126},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.36412814259529114},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.23670470714569092}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8267471790313721},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7690349817276001},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.7582853436470032},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7564013004302979},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.52562016248703},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4970104992389679},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4846280515193939},{"id":"https://openalex.org/C157742956","wikidata":"https://www.wikidata.org/wiki/Q3237776","display_name":"Frequency scaling","level":3,"score":0.4348289966583252},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4283599853515625},{"id":"https://openalex.org/C2776650193","wikidata":"https://www.wikidata.org/wiki/Q264661","display_name":"Obstacle","level":2,"score":0.42794832587242126},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.36412814259529114},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.23670470714569092},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/issoc.2013.6675263","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2013.6675263","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/760659","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/760659","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1686420892","https://openalex.org/W2034062945","https://openalex.org/W2065594723","https://openalex.org/W2095314640","https://openalex.org/W2102727118","https://openalex.org/W2114522727","https://openalex.org/W2118625116","https://openalex.org/W2122195073","https://openalex.org/W2127495914","https://openalex.org/W2135933214","https://openalex.org/W2136994107","https://openalex.org/W2147657366","https://openalex.org/W2151003232","https://openalex.org/W2156391618","https://openalex.org/W2156546318","https://openalex.org/W2157225945","https://openalex.org/W2165576183","https://openalex.org/W2170382128","https://openalex.org/W2541314013","https://openalex.org/W3140062895","https://openalex.org/W3140261852","https://openalex.org/W3140903683","https://openalex.org/W6637151178","https://openalex.org/W6683102158","https://openalex.org/W6792941224"],"related_works":["https://openalex.org/W2794103424","https://openalex.org/W1996530509","https://openalex.org/W3028317537","https://openalex.org/W2389515972","https://openalex.org/W2568855487","https://openalex.org/W2122502560","https://openalex.org/W2625369955","https://openalex.org/W2909257077","https://openalex.org/W2111607776","https://openalex.org/W4362544990"],"abstract_inverted_index":{"Network-on-Chip":[0],"(NoC)":[1],"represents":[2,19],"a":[3,16,20,45,58,80],"flexible":[4,46],"and":[5,11,31,47,94],"scalable":[6,48],"interconnection":[7],"candidate":[8],"for":[9,28,64,98],"current":[10],"future":[12],"multi-cores.":[13],"In":[14,33],"such":[15],"scenario":[17],"power":[18],"major":[21],"design":[22],"obstacle,":[23],"requiring":[24],"accurate":[25],"early-stage":[26,66],"estimation":[27],"both":[29],"cores":[30],"NoCs.":[32],"this":[34],"perspective,":[35],"Dynamic":[36],"Frequency":[37],"Scaling":[38],"(DFS)":[39],"techniques":[40],"have":[41],"been":[42],"proposed":[43],"as":[44,72,74],"way":[49],"to":[50,91],"optimize":[51],"the":[52],"power-performance":[53],"trade-off.":[54],"However,":[55],"there":[56],"is":[57],"lack":[59],"of":[60,68],"tools":[61],"that":[62],"allow":[63],"an":[65],"evaluation":[67],"different":[69],"DFS":[70],"solutions":[71],"well":[73],"asynchronous":[75,86],"NoC.":[76],"This":[77],"work":[78],"proposes":[79],"new":[81],"cycle-accurate":[82],"simulation":[83],"framework":[84],"supporting":[85],"NoC":[87,99],"design,":[88],"allowing":[89],"also":[90],"assess":[92],"heterogeneous":[93],"dynamic":[95],"frequency":[96],"schemes":[97],"routers.":[100]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
