{"id":"https://openalex.org/W2026454041","doi":"https://doi.org/10.1109/issoc.2012.6376354","title":"An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs","display_name":"An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs","publication_year":2012,"publication_date":"2012-10-01","ids":{"openalex":"https://openalex.org/W2026454041","doi":"https://doi.org/10.1109/issoc.2012.6376354","mag":"2026454041"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2012.6376354","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2012.6376354","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031451381","display_name":"Antonio Miele","orcid":"https://orcid.org/0000-0003-3197-0723"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Antonio Miele","raw_affiliation_strings":["Dipartimento Elettronica e Informazione, Politecnico di Milano, Milano, Italy","Politecnico di Milano - Dip. Elettronica e Informazione, P.zza L. da Vinci, 32 - I20133 - Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento Elettronica e Informazione, Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Politecnico di Milano - Dip. Elettronica e Informazione, P.zza L. da Vinci, 32 - I20133 - Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072400487","display_name":"Christian Pilato","orcid":"https://orcid.org/0000-0001-9315-1788"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Christian Pilato","raw_affiliation_strings":["Dipartimento Elettronica e Informazione, Politecnico di Milano, Milano, Italy","Politecnico di Milano - Dip. Elettronica e Informazione, P.zza L. da Vinci, 32 - I20133 - Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento Elettronica e Informazione, Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Politecnico di Milano - Dip. Elettronica e Informazione, P.zza L. da Vinci, 32 - I20133 - Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014181688","display_name":"Donatella Sciuto","orcid":"https://orcid.org/0000-0001-9030-6940"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Donatella Sciuto","raw_affiliation_strings":["Dipartimento Elettronica e Informazione, Politecnico di Milano, Milano, Italy","Politecnico di Milano - Dip. Elettronica e Informazione, P.zza L. da Vinci, 32 - I20133 - Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento Elettronica e Informazione, Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Politecnico di Milano - Dip. Elettronica e Informazione, P.zza L. da Vinci, 32 - I20133 - Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9611272811889648},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8451715707778931},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.7174534201622009},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6999813318252563},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.6019715666770935},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5839718580245972},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5766525268554688},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5604309439659119},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.559822142124176},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.4797743260860443},{"id":"https://openalex.org/keywords/xml","display_name":"XML","score":0.45839086174964905},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.43046998977661133},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.16418898105621338}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9611272811889648},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8451715707778931},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.7174534201622009},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6999813318252563},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6019715666770935},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5839718580245972},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5766525268554688},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5604309439659119},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.559822142124176},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.4797743260860443},{"id":"https://openalex.org/C8797682","wikidata":"https://www.wikidata.org/wiki/Q2115","display_name":"XML","level":2,"score":0.45839086174964905},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.43046998977661133},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.16418898105621338},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/issoc.2012.6376354","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2012.6376354","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/740773","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/740773","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1532503506","https://openalex.org/W2007545650","https://openalex.org/W2120080222","https://openalex.org/W2121845498","https://openalex.org/W2123610036","https://openalex.org/W2123654501","https://openalex.org/W2136770003","https://openalex.org/W2141480229","https://openalex.org/W2148548948","https://openalex.org/W2154635391","https://openalex.org/W2158391679","https://openalex.org/W2538120373","https://openalex.org/W4238404753"],"related_works":["https://openalex.org/W4234221021","https://openalex.org/W2790192245","https://openalex.org/W1973069902","https://openalex.org/W2119904701","https://openalex.org/W2119674509","https://openalex.org/W2576551918","https://openalex.org/W1996984607","https://openalex.org/W2975035977","https://openalex.org/W2533063779","https://openalex.org/W211156700"],"abstract_inverted_index":{"The":[0,86],"efficient":[1],"design":[2,113],"of":[3,46,83],"mapping":[4,71],"solutions":[5,72],"for":[6,34,43,50],"heterogeneous":[7],"Multi-Processor":[8],"Systems-on-Chip":[9],"(MPSoCs)":[10],"is":[11],"usually":[12],"a":[13,30,62,94],"challenging":[14],"task":[15,37],"in":[16,19,61,112],"system-level":[17],"design,":[18],"particular":[20],"when":[21],"the":[22,44,51,56,66,84,104],"architecture":[23],"integrates":[24],"hardware":[25,52],"cores.":[26],"This":[27],"paper":[28],"proposes":[29],"SystemC":[31,47],"simulation":[32],"framework":[33,88],"fulfilling":[35],"this":[36],"featuring":[38],"(i)":[39],"an":[40,76,98,110],"automated":[41],"flow":[42],"generation":[45],"timing":[48],"models":[49],"cores":[53],"starting":[54],"from":[55],"application":[57,101],"source":[58],"code,":[59],"and,":[60],"second":[63],"step,":[64],"(ii)":[65],"possibility":[67,105],"to":[68,93,102,106],"simulate":[69],"different":[70],"simply":[73],"by":[74],"changing":[75],"XML":[77],"descriptor":[78],"and":[79],"without":[80],"any":[81],"interaction":[82],"designer.":[85],"proposed":[87],"has":[89],"been":[90],"then":[91],"applied":[92],"case":[95],"study":[96],"considering":[97],"image":[99],"processing":[100],"present":[103],"integrate":[107],"it":[108],"as":[109],"evaluator":[111],"space":[114],"exploration":[115],"environments.":[116]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
