{"id":"https://openalex.org/W2166926483","doi":"https://doi.org/10.1109/issoc.2012.6376350","title":"Scalability analysis of release and sequential consistency models in NoC based multicore systems","display_name":"Scalability analysis of release and sequential consistency models in NoC based multicore systems","publication_year":2012,"publication_date":"2012-10-01","ids":{"openalex":"https://openalex.org/W2166926483","doi":"https://doi.org/10.1109/issoc.2012.6376350","mag":"2166926483"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2012.6376350","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2012.6376350","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071065914","display_name":"Abdul Naeem","orcid":null},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":true,"raw_author_name":"Abdul Naeem","raw_affiliation_strings":["Department of Electronic Systems, KTH Royal Institute of Technology, Sweden"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Systems, KTH Royal Institute of Technology, Sweden","institution_ids":["https://openalex.org/I86987016"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032163732","display_name":"Axel Jantsch","orcid":"https://orcid.org/0000-0003-2251-0004"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Axel Jantsch","raw_affiliation_strings":["Department of Electronic Systems, KTH Royal Institute of Technology, Sweden"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Systems, KTH Royal Institute of Technology, Sweden","institution_ids":["https://openalex.org/I86987016"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072973899","display_name":"Zhonghai Lu","orcid":"https://orcid.org/0000-0003-0061-3475"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Zhonghai Lu","raw_affiliation_strings":["Department of Electronic Systems, KTH Royal Institute of Technology, Sweden"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Systems, KTH Royal Institute of Technology, Sweden","institution_ids":["https://openalex.org/I86987016"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5071065914"],"corresponding_institution_ids":["https://openalex.org/I86987016"],"apc_list":null,"apc_paid":null,"fwci":0.7451,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.76125396,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.8536080718040466},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7821232676506042},{"id":"https://openalex.org/keywords/consistency","display_name":"Consistency (knowledge bases)","score":0.6491434574127197},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.6463468670845032},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6277762651443481},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5397513508796692},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.5091208815574646},{"id":"https://openalex.org/keywords/execution-time","display_name":"Execution time","score":0.43945884704589844},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.43046507239341736},{"id":"https://openalex.org/keywords/consistency-model","display_name":"Consistency model","score":0.42607903480529785},{"id":"https://openalex.org/keywords/data-consistency","display_name":"Data consistency","score":0.22812223434448242},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21824082732200623},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.162797749042511},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08733919262886047},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.07904085516929626}],"concepts":[{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.8536080718040466},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7821232676506042},{"id":"https://openalex.org/C2776436953","wikidata":"https://www.wikidata.org/wiki/Q5163215","display_name":"Consistency (knowledge bases)","level":2,"score":0.6491434574127197},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6463468670845032},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6277762651443481},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5397513508796692},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.5091208815574646},{"id":"https://openalex.org/C2989134064","wikidata":"https://www.wikidata.org/wiki/Q288510","display_name":"Execution time","level":2,"score":0.43945884704589844},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.43046507239341736},{"id":"https://openalex.org/C37279795","wikidata":"https://www.wikidata.org/wiki/Q2492305","display_name":"Consistency model","level":3,"score":0.42607903480529785},{"id":"https://openalex.org/C93361087","wikidata":"https://www.wikidata.org/wiki/Q4426698","display_name":"Data consistency","level":2,"score":0.22812223434448242},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21824082732200623},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.162797749042511},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08733919262886047},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.07904085516929626},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/issoc.2012.6376350","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2012.6376350","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.259.6770","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.259.6770","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://web.it.kth.se/%7Eaxel/papers/2012/SoCTampere-AbdulNaeem.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1640705102","https://openalex.org/W1769402780","https://openalex.org/W1850405760","https://openalex.org/W1994225686","https://openalex.org/W2027243314","https://openalex.org/W2029601347","https://openalex.org/W2044887272","https://openalex.org/W2050487400","https://openalex.org/W2054739713","https://openalex.org/W2113116043","https://openalex.org/W2127547524","https://openalex.org/W2128771606","https://openalex.org/W2140415683","https://openalex.org/W2150007674","https://openalex.org/W2162468323","https://openalex.org/W2176864362","https://openalex.org/W2999610704","https://openalex.org/W3143472587","https://openalex.org/W3149658335","https://openalex.org/W4236792899","https://openalex.org/W6679200185","https://openalex.org/W6685672314"],"related_works":["https://openalex.org/W118795575","https://openalex.org/W2036306661","https://openalex.org/W1539379314","https://openalex.org/W2138711299","https://openalex.org/W246909719","https://openalex.org/W2044887272","https://openalex.org/W1979030370","https://openalex.org/W2148870314","https://openalex.org/W1906213980","https://openalex.org/W2125934986"],"abstract_inverted_index":{"We":[0],"analyze":[1],"the":[2,5,18,32,38,68,75,78,88,92,96,100,109,113,119,125,131,137,141,152,155],"scalability":[3],"of":[4,34,41,77,136],"Release":[6],"Consistency":[7,11],"(RC)":[8],"and":[9,127],"Sequential":[10],"(SC)":[12],"models":[13],"which":[14,122],"are":[15],"realized":[16],"in":[17,91,151],"Network-on-Chip":[19],"(NoC)":[20],"based":[21,53],"distributed":[22,73],"shared":[23],"memory":[24],"multicore":[25],"systems.":[26],"The":[27,47,63,133],"analysis":[28],"is":[29,81,157],"performed":[30],"on":[31,37,54,124],"basis":[33],"workloads":[35,70],"mapped":[36],"different":[39,44,72],"sizes":[40],"networks":[42],"with":[43],"data":[45],"sets.":[46],"experiments":[48],"use":[49],"a":[50,55],"configurable":[51],"platform":[52],"2D":[56],"mesh":[57],"NoC":[58],"using":[59,71],"deflection":[60],"routing":[61],"algorithm.":[62],"results":[64],"show":[65],"that":[66],"under":[67,112],"synthetic":[69],"locks,":[74],"performance":[76,134],"RC":[79,114,138],"model":[80,90,115,121,139,143],"increased":[82],"by":[83],"17.6%":[84],"to":[85,106,118,130,145],"54.6%":[86],"over":[87,140],"SC":[89,120,142],"64-cores":[93],"system.":[94],"For":[95],"application":[97,126],"workloads,":[98],"as":[99],"network":[101],"size":[102],"grows":[103],"from":[104],"1":[105],"64":[107],"cores,":[108],"execution":[110],"time":[111],"decreases":[116],"relative":[117],"depends":[123],"its":[128],"match":[129],"architecture.":[132],"improvement":[135],"tends":[144],"be":[146],"higher":[147],"than":[148],"50%":[149],"observed":[150],"experiments,":[153],"when":[154],"system":[156],"further":[158],"scaled":[159],"up.":[160]},"counts_by_year":[{"year":2013,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}