{"id":"https://openalex.org/W2036702885","doi":"https://doi.org/10.1109/issoc.2012.6376347","title":"A double data rate 8T-cell SRAM architecture for systems-on-chip","display_name":"A double data rate 8T-cell SRAM architecture for systems-on-chip","publication_year":2012,"publication_date":"2012-10-01","ids":{"openalex":"https://openalex.org/W2036702885","doi":"https://doi.org/10.1109/issoc.2012.6376347","mag":"2036702885"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2012.6376347","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2012.6376347","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091004171","display_name":"Saleh Abdel\u2010hafeez","orcid":"https://orcid.org/0000-0003-2988-1609"},"institutions":[{"id":"https://openalex.org/I156983542","display_name":"Jordan University of Science and Technology","ror":"https://ror.org/03y8mtb59","country_code":"JO","type":"education","lineage":["https://openalex.org/I156983542"]}],"countries":["JO"],"is_corresponding":false,"raw_author_name":"Saleh M. Abdel-Hafeez","raw_affiliation_strings":["Department of Computer Engineering, Jordan University of Science and Technology, Irbid, Jordan","Department of Computer Engineering, Jordan University of Science and Technology, 22110 Irbid, Jordan, P.O.BOX 3030"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Jordan University of Science and Technology, Irbid, Jordan","institution_ids":["https://openalex.org/I156983542"]},{"raw_affiliation_string":"Department of Computer Engineering, Jordan University of Science and Technology, 22110 Irbid, Jordan, P.O.BOX 3030","institution_ids":["https://openalex.org/I156983542"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010203738","display_name":"Mohamad Shatnawi","orcid":"https://orcid.org/0000-0003-1030-9485"},"institutions":[{"id":"https://openalex.org/I156983542","display_name":"Jordan University of Science and Technology","ror":"https://ror.org/03y8mtb59","country_code":"JO","type":"education","lineage":["https://openalex.org/I156983542"]}],"countries":["JO"],"is_corresponding":false,"raw_author_name":"Mohammad Shatnawi","raw_affiliation_strings":["Department of Computer Engineering, Jordan University of Science and Technology, Irbid, Jordan","Department of Computer Engineering, Jordan University of Science and Technology, 22110 Irbid, Jordan, P.O.BOX 3030"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Jordan University of Science and Technology, Irbid, Jordan","institution_ids":["https://openalex.org/I156983542"]},{"raw_affiliation_string":"Department of Computer Engineering, Jordan University of Science and Technology, 22110 Irbid, Jordan, P.O.BOX 3030","institution_ids":["https://openalex.org/I156983542"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035415168","display_name":"Ann Gordon-Ross","orcid":"https://orcid.org/0000-0001-8865-8381"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ann Gordon-Ross","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","Department of Electrical and Computer Engineering, University of Florida, Gainesville, 32611, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, 32611, USA#TAB#","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7689075469970703},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7342160940170288},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5550998449325562},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.5291253328323364},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5284616351127625},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5273260474205017},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5212298631668091},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4480043053627014},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.43030375242233276},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.42969322204589844},{"id":"https://openalex.org/keywords/signal-edge","display_name":"Signal edge","score":0.42159345746040344},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14474719762802124},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.13466587662696838},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11891824007034302},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10737648606300354},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07941854000091553}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7689075469970703},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7342160940170288},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5550998449325562},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.5291253328323364},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5284616351127625},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5273260474205017},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5212298631668091},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4480043053627014},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.43030375242233276},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.42969322204589844},{"id":"https://openalex.org/C117525741","wikidata":"https://www.wikidata.org/wiki/Q775654","display_name":"Signal edge","level":4,"score":0.42159345746040344},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14474719762802124},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.13466587662696838},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11891824007034302},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10737648606300354},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07941854000091553},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/issoc.2012.6376347","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2012.6376347","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8199999928474426,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W156735343","https://openalex.org/W1567119267","https://openalex.org/W1877467149","https://openalex.org/W2031342191","https://openalex.org/W2105175332","https://openalex.org/W2106507957","https://openalex.org/W2109104675","https://openalex.org/W2133916413","https://openalex.org/W2145483219","https://openalex.org/W2187738622","https://openalex.org/W2397682474"],"related_works":["https://openalex.org/W2119025037","https://openalex.org/W2362169398","https://openalex.org/W2139353707","https://openalex.org/W3083915265","https://openalex.org/W2102669059","https://openalex.org/W1644931186","https://openalex.org/W2505475684","https://openalex.org/W4285153061","https://openalex.org/W2288705349","https://openalex.org/W2893412776"],"abstract_inverted_index":{"The":[0],"substantial":[1],"increase":[2],"in":[3],"market":[4],"demand":[5],"for":[6,12,18],"handheld":[7],"devices":[8],"drives":[9],"the":[10,76,82,86,92,96,106,115,121],"need":[11],"low-power":[13,28],"high-speed":[14],"data":[15,37,163],"access":[16],"SRAM":[17,29,135],"systems-on-chip":[19],"(SoCs).":[20],"In":[21],"this":[22],"paper,":[23],"we":[24],"present":[25],"a":[26,43,47,131,144,158,162],"novel":[27],"architectural":[30,49],"design":[31],"that":[32,75,105,153],"provides":[33],"high-noise":[34],"margin":[35],"double":[36],"rate":[38],"(DDR)":[39],"read/write":[40,160],"accesses":[41,68,98,138],"using":[42,143],"conventional":[44],"8T-Cell":[45,141],"and":[46,54,60,85,126,139,167],"partitioned":[48],"structure":[50,142],"consisting":[51],"of":[52,165,172],"even":[53,59,77,107],"odd":[55,61,87,122],"modules":[56,78,88,108,123],"(corresponding":[57],"to":[58,111],"addresses),":[62],"which":[63],"are":[64,79,89,109,124],"accessed":[65,80,90],"alternatingly.":[66],"Write":[67],"occur":[69,99],"at":[70,81,91,100,114],"both":[71,101],"clock":[72,102,117],"edges":[73,103],"such":[74,104],"rising":[83,116],"edge":[84],"falling":[93],"edge.":[94],"Similarly,":[95],"read":[97],"assumed":[110],"be":[112],"evaluated":[113],"edge,":[118],"while":[119],"concurrently":[120],"pre-charged,":[125],"vice":[127],"versa.":[128],"We":[129],"implement":[130],"128-bit":[132],"\u00d7":[133],"64-bit":[134],"with":[136,157],"DDR":[137],"an":[140,168],"standard":[145],"0.09\u03bcm/1V":[146],"CMOS":[147],"TSMC":[148],"process.":[149],"Simulation":[150],"results":[151],"reveal":[152],"our":[154],"architecture":[155],"operates":[156],"1GHz":[159],"cycle,":[161],"throughput":[164],"2GHz/64-bit,":[166],"average":[169],"power":[170],"consumption":[171],"23.4mW.":[173]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}