{"id":"https://openalex.org/W2073767541","doi":"https://doi.org/10.1109/issoc.2011.6089695","title":"Mismatch characterization of high-speed NoC links using asynchronous sub-sampling","display_name":"Mismatch characterization of high-speed NoC links using asynchronous sub-sampling","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2073767541","doi":"https://doi.org/10.1109/issoc.2011.6089695","mag":"2073767541"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2011.6089695","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2011.6089695","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050298468","display_name":"Sebastian H\u00f6ppner","orcid":"https://orcid.org/0000-0002-9938-2736"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Sebastian Hoppner","raw_affiliation_strings":["Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Dresden, Germany","Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Germany#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Germany#TAB#","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091157874","display_name":"Dennis Walter","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dennis Walter","raw_affiliation_strings":["Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Dresden, Germany","Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Germany#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Germany#TAB#","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059380044","display_name":"Georg Ellguth","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Georg Ellguth","raw_affiliation_strings":["Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Dresden, Germany","Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Germany#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Germany#TAB#","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110046407","display_name":"Ren\u00e9 Sch\u00fcffny","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rene Schuffny","raw_affiliation_strings":["Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Dresden, Germany","Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Germany#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Faculty of Electrical Engineering and Information Technology, Technische Universit\u00e4t Dresden, Germany#TAB#","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"112","last_page":"115"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7277923822402954},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7040478587150574},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6378856897354126},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.6216243505477905},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.570205569267273},{"id":"https://openalex.org/keywords/sampling","display_name":"Sampling (signal processing)","score":0.4824431538581848},{"id":"https://openalex.org/keywords/gigabit","display_name":"Gigabit","score":0.4702925682067871},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4653618633747101},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4635910391807556},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.445720374584198},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.44138187170028687},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.42456483840942383},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35236847400665283},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33684980869293213},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17588865756988525},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.14385199546813965},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.07627397775650024}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7277923822402954},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7040478587150574},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6378856897354126},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.6216243505477905},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.570205569267273},{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.4824431538581848},{"id":"https://openalex.org/C21922175","wikidata":"https://www.wikidata.org/wiki/Q3105497","display_name":"Gigabit","level":2,"score":0.4702925682067871},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4653618633747101},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4635910391807556},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.445720374584198},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.44138187170028687},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.42456483840942383},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35236847400665283},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33684980869293213},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17588865756988525},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14385199546813965},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.07627397775650024},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/issoc.2011.6089695","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2011.6089695","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5299999713897705,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321114","display_name":"Bundesministerium f\u00fcr Bildung und Forschung","ror":"https://ror.org/04pz7b180"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2046317813","https://openalex.org/W2094340265","https://openalex.org/W2098808037","https://openalex.org/W2103692532","https://openalex.org/W2125154572","https://openalex.org/W2153492262","https://openalex.org/W2157887705","https://openalex.org/W6683104957"],"related_works":["https://openalex.org/W1976012348","https://openalex.org/W2560375935","https://openalex.org/W2614713859","https://openalex.org/W2002682434","https://openalex.org/W2039453232","https://openalex.org/W4387782849","https://openalex.org/W2144357574","https://openalex.org/W4230458348","https://openalex.org/W1966325333","https://openalex.org/W3198758847"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"asynchronous":[3],"sub-sampling":[4],"techniques":[5,22,61],"to":[6,31,51,80],"measure":[7],"delay":[8,49],"mismatch":[9],"of":[10,26,48,69,83,85],"clock":[11],"and":[12],"data":[13],"lanes":[14],"in":[15,72],"high-speed":[16,53],"serial":[17],"network-on-chip":[18],"(NoC)":[19],"links.":[20,44],"The":[21,59],"allow":[23],"the":[24,77],"use":[25],"low":[27],"quality":[28],"sampling":[29],"clocks":[30],"reduce":[32],"test":[33],"hardware":[34],"overhead":[35],"for":[36],"integration":[37],"into":[38],"complex":[39],"MPSoCs":[40],"with":[41,56],"multiple":[42],"NoC":[43,54,65],"It":[45],"enables":[46],"compensation":[47],"variations":[50],"realize":[52],"links":[55,66],"sufficient":[57],"yield.":[58],"proposed":[60],"are":[62],"demonstrated":[63],"at":[64],"as":[67],"part":[68],"an":[70],"MPSoC":[71],"65nm":[73],"CMOS":[74],"technology,":[75],"where":[76],"calibration":[78],"leads":[79],"significant":[81],"reduction":[82],"bit-error-rates":[84],"a":[86],"72":[87],"GBit/s":[88,90],"(8":[89],"per":[91],"lane)":[92],"link":[93],"over":[94],"4mm":[95],"on-chip":[96],"interconnect.":[97]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}