{"id":"https://openalex.org/W1981318072","doi":"https://doi.org/10.1109/issoc.2011.6089691","title":"Exploring instruction caching strategies for tightly-coupled shared-memory clusters","display_name":"Exploring instruction caching strategies for tightly-coupled shared-memory clusters","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W1981318072","doi":"https://doi.org/10.1109/issoc.2011.6089691","mag":"1981318072"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2011.6089691","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2011.6089691","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/11380/1171836","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020213779","display_name":"Daniele Bortolotti","orcid":"https://orcid.org/0000-0002-2175-2418"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Daniele Bortolotti","raw_affiliation_strings":["Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), University of Bologna, Bologna, Italy","Dipartimento di Elettronica, Informatica e Sistemistica (DEIS) - University of Bologna, Viale Risorgimento, 2 - 40135, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica (DEIS) - University of Bologna, Viale Risorgimento, 2 - 40135, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010034275","display_name":"Francesco Paterna","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Francesco Paterna","raw_affiliation_strings":["Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), University of Bologna, Bologna, Italy","Dipartimento di Elettronica, Informatica e Sistemistica (DEIS) - University of Bologna, Viale Risorgimento, 2 - 40135, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica (DEIS) - University of Bologna, Viale Risorgimento, 2 - 40135, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031211716","display_name":"Christian Pinto","orcid":"https://orcid.org/0000-0001-7060-2742"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Christian Pinto","raw_affiliation_strings":["Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), University of Bologna, Bologna, Italy","Dipartimento di Elettronica, Informatica e Sistemistica (DEIS) - University of Bologna, Viale Risorgimento, 2 - 40135, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica (DEIS) - University of Bologna, Viale Risorgimento, 2 - 40135, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061145921","display_name":"Andrea Marongiu","orcid":"https://orcid.org/0000-0003-1010-4762"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Marongiu","raw_affiliation_strings":["Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), University of Bologna, Bologna, Italy","Dipartimento di Elettronica, Informatica e Sistemistica (DEIS) - University of Bologna, Viale Risorgimento, 2 - 40135, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica (DEIS) - University of Bologna, Viale Risorgimento, 2 - 40135, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062549550","display_name":"Martino Ruggiero","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Martino Ruggiero","raw_affiliation_strings":["Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), University of Bologna, Bologna, Italy","Dipartimento di Elettronica, Informatica e Sistemistica (DEIS) - University of Bologna, Viale Risorgimento, 2 - 40135, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica (DEIS) - University of Bologna, Viale Risorgimento, 2 - 40135, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), University of Bologna, Bologna, Italy","Dipartimento di Elettronica, Informatica e Sistemistica (DEIS) - University of Bologna, Viale Risorgimento, 2 - 40135, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica (DEIS) - University of Bologna, Viale Risorgimento, 2 - 40135, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5020213779"],"corresponding_institution_ids":["https://openalex.org/I9360294"],"apc_list":null,"apc_paid":null,"fwci":2.5758,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.897993,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"34","last_page":"41"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8520379662513733},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6196982860565186},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5726721286773682},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.5587208867073059},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.5527750253677368},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.544196367263794},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4898781180381775},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.48421359062194824},{"id":"https://openalex.org/keywords/fetch","display_name":"Fetch","score":0.45788490772247314},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.4215683341026306},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.35537195205688477},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2096344232559204},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.16113993525505066}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8520379662513733},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6196982860565186},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5726721286773682},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.5587208867073059},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.5527750253677368},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.544196367263794},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4898781180381775},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.48421359062194824},{"id":"https://openalex.org/C131918245","wikidata":"https://www.wikidata.org/wiki/Q1409090","display_name":"Fetch","level":2,"score":0.45788490772247314},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.4215683341026306},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.35537195205688477},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2096344232559204},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.16113993525505066},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C111368507","wikidata":"https://www.wikidata.org/wiki/Q43518","display_name":"Oceanography","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/issoc.2011.6089691","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2011.6089691","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.650.5607","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.650.5607","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www-micrel.deis.unibo.it/aigaion2/attachments/soc11.pdf-2811d0c40deb5f76ef1b621bbf94a8f3.pdf","raw_type":"text"},{"id":"pmh:oai:cris.unibo.it:11585/109155","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/109155","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:iris.unimore.it:11380/1171836","is_oa":true,"landing_page_url":"http://hdl.handle.net/11380/1171836","pdf_url":null,"source":{"id":"https://openalex.org/S4377196326","display_name":"Iris Unimore (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:iris.unimore.it:11380/1171836","is_oa":true,"landing_page_url":"http://hdl.handle.net/11380/1171836","pdf_url":null,"source":{"id":"https://openalex.org/S4377196326","display_name":"Iris Unimore (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2041997506","https://openalex.org/W2110195531","https://openalex.org/W2132829148"],"related_works":["https://openalex.org/W2145592252","https://openalex.org/W2118508246","https://openalex.org/W2134439766","https://openalex.org/W2407815036","https://openalex.org/W4255008187","https://openalex.org/W4250205214","https://openalex.org/W2036306661","https://openalex.org/W2143087414","https://openalex.org/W1797968800","https://openalex.org/W2105141138"],"abstract_inverted_index":{"Several":[0],"Chip-Multiprocessor":[1],"designs":[2],"today":[3],"leverage":[4],"tightly-coupled":[5],"computing":[6],"clusters":[7,13],"as":[8],"a":[9,16,28,99,115],"building":[10],"block.":[11],"These":[12],"consist":[14],"of":[15,21,102,128,137],"fairly":[17],"large":[18],"number":[19],"N":[20],"simple":[22],"cores,":[23],"featuring":[24],"fast":[25],"communication":[26],"through":[27],"shared":[29,92],"multibanked":[30],"L1":[31],"data":[32],"memory":[33],"and":[34,90,141,150],"\u2248":[35],"1":[36],"Instruction-Per-Cycle":[37],"(IPC)":[38],"per":[39,88,95],"core.":[40],"Thus,":[41],"aggregated":[42],"I-fetch":[43,66],"bandwidth":[44],"approaches":[45],"f":[46,50],"*":[47],"N,":[48],"where":[49],"is":[51,61],"the":[52,103,129,135],"cluster":[53,106],"clock":[54],"frequency.":[55],"An":[56],"effective":[57],"instruction":[58,77,86,93],"cache":[59,94],"architecture":[60],"key":[62],"to":[63],"support":[64],"this":[65,69],"bandwidth.":[67],"In":[68],"paper":[70],"we":[71],"compare":[72],"two":[73,130],"main":[74],"architectures":[75],"for":[76,112,152],"caching":[78],"targeting":[79],"tightly":[80,104],"coupled":[81,105],"CMP":[82],"clusters:":[83],"(i)":[84],"private":[85],"caches":[87],"core":[89],"(ii)":[91],"cluster.":[96],"We":[97,123],"developed":[98],"cycle-accurate":[100],"model":[101],"with":[107],"several":[108],"configurable":[109],"architectural":[110,131],"parameters":[111],"exploration,":[113],"plus":[114],"programming":[116],"environment":[117],"targeted":[118],"at":[119],"efficient":[120],"data-parallel":[121],"computing.":[122],"conduct":[124],"an":[125],"in-depth":[126],"study":[127],"templates":[132],"based":[133],"on":[134],"use":[136],"both":[138],"synthetic":[139],"microbenchmarks":[140],"real":[142],"program":[143],"workloads.":[144],"Our":[145],"results":[146],"provide":[147],"useful":[148],"insights":[149],"guidelines":[151],"designers.":[153]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-05T09:01:59.212387","created_date":"2025-10-10T00:00:00"}
