{"id":"https://openalex.org/W2012430078","doi":"https://doi.org/10.1109/issoc.2011.6089685","title":"Customizable Datapath Integrated Lock Unit","display_name":"Customizable Datapath Integrated Lock Unit","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2012430078","doi":"https://doi.org/10.1109/issoc.2011.6089685","mag":"2012430078"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2011.6089685","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2011.6089685","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050272735","display_name":"Pekka J\u00e4\u00e4skel\u00e4inen","orcid":"https://orcid.org/0000-0001-5707-8544"},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Pekka Jaaskelainen","raw_affiliation_strings":["Department of Computer Systems, Tampere University of Technology, Tampere, Finland","Tampere University of Technology / Department of Computer Systems, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Tampere University of Technology / Department of Computer Systems, Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078390067","display_name":"Erno Salminen","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Erno Salminen","raw_affiliation_strings":["Department of Computer Systems, Tampere University of Technology, Tampere, Finland","Tampere University of Technology / Department of Computer Systems, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Tampere University of Technology / Department of Computer Systems, Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079200816","display_name":"Otto Esko","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Otto Esko","raw_affiliation_strings":["Department of Computer Systems, Tampere University of Technology, Tampere, Finland","Tampere University of Technology / Department of Computer Systems, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Tampere University of Technology / Department of Computer Systems, Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070892606","display_name":"Jarmo Takala","orcid":"https://orcid.org/0000-0003-0097-1010"},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Jarmo Takala","raw_affiliation_strings":["Department of Computer Systems, Tampere University of Technology, Tampere, Finland","Tampere University of Technology / Department of Computer Systems, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Tampere University of Technology / Department of Computer Systems, Finland","institution_ids":["https://openalex.org/I4210133110"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5153,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.65694035,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"18","issue":null,"first_page":"29","last_page":"33"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.8995475769042969},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8429309129714966},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.7015970945358276},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.675567090511322},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5999743938446045},{"id":"https://openalex.org/keywords/lock","display_name":"Lock (firearm)","score":0.526877224445343},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.494615763425827},{"id":"https://openalex.org/keywords/template","display_name":"Template","score":0.485376238822937},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4841404855251312},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.4819645583629608},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.4748544692993164},{"id":"https://openalex.org/keywords/task-parallelism","display_name":"Task parallelism","score":0.4504221975803375},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42492133378982544},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.167030930519104},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.06691548228263855}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.8995475769042969},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8429309129714966},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.7015970945358276},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.675567090511322},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5999743938446045},{"id":"https://openalex.org/C174839445","wikidata":"https://www.wikidata.org/wiki/Q1134386","display_name":"Lock (firearm)","level":2,"score":0.526877224445343},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.494615763425827},{"id":"https://openalex.org/C82714645","wikidata":"https://www.wikidata.org/wiki/Q438331","display_name":"Template","level":2,"score":0.485376238822937},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4841404855251312},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.4819645583629608},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.4748544692993164},{"id":"https://openalex.org/C42992933","wikidata":"https://www.wikidata.org/wiki/Q691169","display_name":"Task parallelism","level":3,"score":0.4504221975803375},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42492133378982544},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.167030930519104},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.06691548228263855},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/issoc.2011.6089685","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2011.6089685","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Symposium on System on Chip (SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1751719679","https://openalex.org/W1963637299","https://openalex.org/W2001738739","https://openalex.org/W2018307252","https://openalex.org/W2069278684","https://openalex.org/W2098683869","https://openalex.org/W2107716502","https://openalex.org/W2131591470","https://openalex.org/W2169248084","https://openalex.org/W3151570535","https://openalex.org/W4255374472","https://openalex.org/W6674664704","https://openalex.org/W6675959653"],"related_works":["https://openalex.org/W2162921448","https://openalex.org/W2950520577","https://openalex.org/W2100984465","https://openalex.org/W74409296","https://openalex.org/W2003935582","https://openalex.org/W1554644772","https://openalex.org/W305742777","https://openalex.org/W2940653809","https://openalex.org/W2567390125","https://openalex.org/W2468095077"],"abstract_inverted_index":{"Multicore":[0],"Application-Specific":[1],"Instruction-Set":[2],"Processors":[3],"(MCASIP)":[4],"offer":[5],"an":[6],"interesting":[7],"alternative":[8],"for":[9],"implementing":[10],"parallel":[11],"applications":[12],"in":[13],"MPSoCs.":[14],"Flexible":[15],"MCASIP":[16],"architecture":[17],"templates":[18],"allow":[19],"matching":[20],"the":[21,29,32,35],"instruction":[22],"and":[23],"task":[24],"level":[25],"parallelism":[26],"provided":[27],"by":[28],"processor":[30],"to":[31],"requirements":[33],"of":[34],"application":[36],"at":[37],"hand.":[38]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}